IS61LPS51218A_12 Datasheet, PDF (29/35 Pages) Integrated Silicon Solution, Inc – 256K x 36, 256K x 32, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM

IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
165 PBGA BOUNDARY SCAN ORDER (x 18)

Bit #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Signal Bump
Name ID
MODE 1R
NC 6N
A 11P
A
8P
A
8R
A
9R
A
9P
A 10P
A 10R
A 11R
ZZ 11H
NC 11N
NC 11M
NC 11L
NC 11K
NC 11J
DQa 10M
DQa 10L
DQa 10K
DQa 10J
Bit #
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Signal
Name
DQa
DQa
DQa
DQa
DQa
NC
NC
NC
NC
A
A
A
ADV
ADSP
ADSC
OE
BWE
GW
CLK
NC
Bump
ID
Bit #
11G
41
11F
42
11E
43
11D
44
11C
45
10F
46
10E
47
10D
48
10G
49
11A
50
10A
51
10B
52
9A
53
9B
54
8A
55
8B
56
7A
57
7B
58
6B
59
11B
60
Signal
Name
NC
CE2
BWa
NC
BWb
NC
CE2
CE
A
A
NC
NC
NC
NC
NC
NC
DQb
DQb
DQb
DQb
Bump
ID
1A
6A
5B
5A
4A
4B
3B
3A
2A
2B
1B
1C
1D
1E
1F
1G
2D
2E
2F
2G
Bit #
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
Signal
Name
DQb
DQb
DQb
DQb
DQb
NC
NC
NC
NC
A
A
A
A
A1
A0
Bump
ID
1J
1K
1L
1M
1N
2K
2L
2M
2J
3P
3R
4R
4P
6P
6R
Integrated Silicon Solution, Inc.
29
Rev. L
09/06/12