IS61LPS51218A_12 Datasheet, PDF (5/35 Pages) Integrated Silicon Solution, Inc – 256K x 36, 256K x 32, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM

IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
119 BGA PACKAGE PIN CONFIGURATION
512Kx18 (TOP VIEW)
1
2
3
4
A
VDDQ
A
A
ADSP
B
NC
CE2
A
ADSC
C
NC
A
A
VDD
D
DQb
NC
Vss
NC
E
NC
DQb
Vss
CE
F
VDDQ
NC
Vss
OE
G
NC
DQb
BWb
ADV
H
DQb
NC
Vss
GW
J
VDDQ
VDD
NC
VDD
K
NC
DQb
Vss
CLK
L
DQb
NC
Vss
NC
M
VDDQ
DQb
Vss
BWE
N
DQb
NC
Vss
A1*
P
NC
DQPb
Vss
A0*
R
NC
A
MODE
VDD
T
NC
A
A
NC
U
VDDQ
TMS
TDI
TCK
5
A
A
A
Vss
Vss
Vss
Vss
Vss
NC
Vss
BWa
Vss
Vss
Vss
NC
A
TDO
6
A
A
A
DQPa
NC
DQa
NC
DQa
VDD
NC
DQa
NC
DQa
NC
A
A
NC
7
VDDQ
NC
NC
NC
DQa
VDDQ
DQa
NC
VDDQ
DQa
NC
VDDQ
NC
DQa
NC
ZZ
VDDQ
Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
A
A0, A1
ADV
ADSP
ADSC
GW
CLK
CE, CE2
BWx (x=a,b)
BWE
Pin Name
Address Inputs
Synchronous Burst Address Inputs
Synchronous Burst Address
Advance
Address Status Processor
Address Status Controller
Global Write Enable
Synchronous Clock
Synchronous Chip Select
Synchronous Byte Write Controls
Byte Write Enable
Symbol
OE
ZZ
MODE
TCK, TDO
TMS, TDI
NC
DQa-DQb
DQPa-Pb
Vdd
Vddq
Vss
Pin Name
Output Enable
Power Sleep Mode
Burst Sequence Selection
JTAG Pins
No Connect
Data Inputs/Outputs
Output Power Supply
Power Supply
Output Power Supply
Ground
Integrated Silicon Solution, Inc.
5
Rev. L
09/06/12