IS61LPS51218A_12 Datasheet, PDF (25/35 Pages) Integrated Silicon Solution, Inc – 256K x 36, 256K x 32, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM

IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
TAP Electrical Characteristics Over the Operating Range^(1,2)
Symbol
Parameter
Test Conditions
Min.
Max.
Voh1
Output HIGH Voltage
Ioh = –2.0 mA
1.7
—
Voh2
Output HIGH Voltage
Ioh = –100 µA
2.1
—
Vol1
Output LOW Voltage
Iol = 2.0 mA
—
0.7
Vol2
Output LOW Voltage
Iol = 100 µA
—
0.2
Vih
Input HIGH Voltage 1.7 Vdd +0.3
Vil
Input LOW Voltage –0.3 0.7
Ix
Input Leakage Current
Vss ≤ V I ≤ Vddq
Notes:
1. All Voltage referenced to Ground.
2. Overshoot: Vih (AC) ≤Vdd +1.5V for t ≤ ttcyc/2,
Undershoot: Vil (AC) ≥ -1.5V for t ≤ ttcyc/2,
Power-up: Vih < 2.6V and Vdd < 2.4V and Vddq < 1.4V for t < 200 ms.
–10
10
Units
V
V
V
V
V
V
µA
TAP AC ELECTRICAL CHARACTERISTICS^(1,2) (OVER OPERATING RANGE)
Symbol Parameter Min.
Max.
Unit
ttcyc TCK Clock cycle time 100
—
ns
ftf
TCK Clock frequency
—
10
MHz
tth
TCK Clock HIGH 40 —
ns
ttl
TCK Clock LOW
40
—
ns
ttmss TMS setup to TCK Clock Rise 10
—
ns
ttdis
TDI setup to TCK Clock Rise 10
—
ns
tcs
Capture setup to TCK Rise 10
—
ns
ttmsh TMS hold after TCK Clock Rise 10 — ns
ttdih
TDI Hold after Clock Rise 10
—
ns
tch
Capture hold after Clock Rise 10
—
ns
ttdov TCK LOW to TDO valid
—
20
ns
ttdox TCK LOW to TDO invalid 0
—
ns
Notes:
1. Both tcs and tch refer to the set-up and hold time requirements of latching data from the boundary scan register.
2. Test conditions are specified using the load in TAP AC test conditions. tr/tf = 1 ns.
Integrated Silicon Solution, Inc.
25
Rev. L
09/06/12