IS66WVC4M16ALL Datasheet, PDF (62/67 Pages) Integrated Silicon Solution, Inc – Mixed Mode supports asynchronous write and synchronous read operation

IS66WVC4M16ALL
IS67WVC4M16ALL
Figure 47: Burst READ Followed by Asynchronous WRITE (WE#-Controlled)
t_ABA
t_CLK
CLK
Address
DQ0-
DQ15
VALID
ADDRESS
t_SP t_HD
t_ACLK
t_KOH
VALID
OUTPUT
ADV#
t_SP t_HD
t_CSP
t_CEM
t_HD
CE#
t_WC
t_AW
t_WR
VALID
ADDRESS
t_AS t_WHZ
t_DW
t_DH
VALID
DATA
t_LZ
t_CW
t_SP
t_HD
t_BW
UB#/LB#
WE#
t_OLZ
OE#
t_CEW
WAIT ^HiZ
t_BOE
t_HZ
t_KHTL
t_WP
t_CEW
t_HZ
HiZ
Notes:
1. Non-default BCR settings for burst READ followed by asynchronous WE#-controlled WRITE:
fixed or variable latency; latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay.
2. When transitioning between asynchronous and variable-latency burst operations, CE# must
go HIGH. CE# can stay LOW when transitioning from fixed-latency burst READs. A refresh
opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the
following two conditions: a) clocked CE# HIGH or b) CE# HIGH for longer than 15ns.
Rev. B | July 2012
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