IS66WVC4M16ALL Datasheet, PDF (14/67 Pages) Integrated Silicon Solution, Inc – Mixed Mode supports asynchronous write and synchronous read operation

IS66WVC4M16ALL
IS67WVC4M16ALL
Mixed-Mode Operation
The device can support a combination of synchronous READ and asynchronous READ
and WRITE operations when the BCR is configured for synchronous operation. The
asynchronous READ and WRITE operations require that the clock (CLK) remain LOW
during the entire sequence. The ADV# signal can be used to latch the target address,
or it can remain LOW during the entire WRITE operation. CE# can remain LOW
when transitioning between mixed-mode operations with fixed latency enabled;
however, the CE# LOW time must not exceed tCEM. Mixed-mode operation facilitates a
seamless interface to legacy burst mode Flash memory controllers. See Figure 45 for the
“Asynchronous WRITE Followed by Burst READ” timing diagram.
WAIT Operation
WAIT output on the CellularRAM device is typically connected to a shared, system-level
WAIT signal. The shared WAIT signal is used by the processor to coordinate transactions
with multiple memories on the synchronous bus.
When a synchronous READ or WRITE operation has been initiated, WAIT goes active to
indicate that the CellularRAM device requires additional time before data can be
transferred. For READ operations, WAIT will remain active until valid data is output
from the device. For WRITE operations, WAIT will indicate to the memory controller
when data will be accepted into the CellularRAM device. When WAIT transitions to an
inactive state, the data burst will progress on successive rising clock edges.
During a burst cycle CE# must remain asserted until the first data is valid. Bringing CE#
HIGH during this initial latency may cause data corruption.
When using variable initial access latency (BCR[14] = 0), the WAIT output performs an
arbitration role for READ operations launched while an on-chip refresh is in progress. If
a collision occurs, the WAIT pin is asserted for additional clock cycles until the refresh
has completed (see Figure 26). When the refresh operation has completed, the
READ operation will continue normally.
WAIT will be asserted but should be ignored during asynchronous READ and WRITE and
page READ operations.
WAIT will be High-Z during asynchronous WRITE operations.
By using fixed initial latency (BCR[14] = 1), this CellularRAM device can be used in burst
mode without monitoring the WAIT pin. However, WAIT can still be used to determine
when valid data is available at the start of the burst and at the end of the row. If wait is
not monitored, the controller must stop burst accesses at row boundaries on its own.
UB#/LB# Operation
The UB#/LB# enable signals support byte-wide data WRITEs. During WRITE operations,
any disabled bytes will not be transferred to the RAM array and the internal value will
remain unchanged. During an asynchronous WRITE cycle, the data to be written is
latched on the rising edge of CE#, WE#, UB#, and LB# whichever occurs first.
UB#/LB# must be LOW during synchronous READ cycles.
When UB#/LB# are disabled (HIGH) during an operation, the device will disable the data
bus from receiving or transmitting data. Although the device will seem to be deselected,
it remains in an active mode as long as CE# remains LOW.
Rev. B | July 2012
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