IS66WVC4M16ALL Datasheet, PDF (32/67 Pages) Integrated Silicon Solution, Inc – Mixed Mode supports asynchronous write and synchronous read operation

IS66WVC4M16ALL
IS67WVC4M16ALL
Table16 . Burst READ Cycle Timing Requirements
Symbol
Parameter
-7010
-7008
Unit Note
Min Max Min Max
t_AA
Address Acess Time (Fixed Latency)
70
70
ns
t_AADV ADV# Access Time (Fixed Latency)
70
70
ns
t_ABA
Burst to READ Access Time
(Variable Latency)
35.9
46.5 ns
t_ACLK
CLK to Output Delay
t_AVH
Address hold from ADV# HIGH
(Fixed Latency)
7
9
ns
2
2
ns
t_BOE
t_CBPH
Burst OE# LOW to Output Valid
CE# High between Subsequent
Burst or Mixed-Mode Operations
20
20
ns
5
6
ns
1
t_CEM
Maximum CE# Pulse width
4
4
us
1
t_CEW
CE# low to WAIT Valid
t_CLK
CLK Period
t_CO
Chip Select Access Time (Fixed
Latency)
1
7.5
1
7.5
ns
9.62
12.5
ns
70
70
ns
t_CSP
CE# Setup Time to Active CLK Edge 3
4
ns
t_HD
Hold Time from Active CLK Edge
2
2
ns
t_HZ
Chip Disable to DQ and WAIT
High-Z Output
8
8
ns
2
t_KHKL
CLK rise or fall Time
1.6
1.8
ns
t_KHTL
CLK to WAIT Valid
7
9
ns
t_KOH
Output HOLD from CLK
2
2
t_KP
CLK HIGH or LOW time
3
4
t_OHZ
Output disable to DQ High-Z Output
8
8
ns
2
t_OLZ
Output enable to DQ Low-Z output
3
3
ns
3
t_SP
Setup time to Active CLK Edge
3
3
ns
Notes:
1. A refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by
either of the following two conditions : a) clocked CE#, or b) CE# HIGH for longer than 15ns
2. Low-Z to High-Z timings are tested with the circuit shown in Figure 17.
The High-Z timings measure a 100mV transition from either VOH or VOL toward VDDQ/2.
3. High-Z to Low-Z timings are tested with the circuit shown in Figure 17. The
Low-Z timings measure a 100mV transition away from the High-Z (VDDQ/2) level toward
either VOH or VOL.
Rev. B | July 2012
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