IS66WVC4M16ALL Datasheet, PDF (34/67 Pages) Integrated Silicon Solution, Inc – Mixed Mode supports asynchronous write and synchronous read operation

IS66WVC4M16ALL
IS67WVC4M16ALL
Table18 . Burst WRITE Cycle Timing Requirements
Symbol
Parameter
t_AS
t_AVH
t_CBPH
t_CEM
t_CEW
t_CLK
t_CSP
t_HD
t_HZ
t_KHKL
t_KHTL
t_KP
t_SP
Address and ADV# LOW Setup
Time
Address hold from ADV# HIGH
(Fixed Latency)
CE# High between Subsequent
Burst or Mixed-Mode Operations
Maximum CE# Pulse width
CE# low to WAIT Valid
CLK Period
CE# Setup Time to Active CLK
Edge
Hold Time from Active CLK Edge
Chip Disable to DQ and WAIT
High-Z Output
CLK rise or fall Time
CLK to WAIT Valid
CLK HIGH or LOW time
Setup time to Active CLK Edge
-7010
Min Max
-7008
Min Max
0
0
2
2
5
6
4
4
1
7.5
1
7.5
9.62
12.5
3
4
2
2
8
8
1.6
1.8
7
9
3
4
3
3
Unit Note
ns
1
ns
ns
2
us
2
ns
ns
ns
ns
ns
3
ns
ns
ns
ns
Notes:
1. tAS required if tCSP > 20ns.
2. A refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by
either of the following two conditions : a) clocked CE#, or b) CE# HIGH for longer than 15ns
3. Low-Z to High-Z timings are tested with the circuit shown in Figure 17.
The High-Z timings measure a 100mV transition from either VOH or VOL toward VDDQ/2.
Table19 . Initialization and DPD Timing Requirements
Symbol
Parameter
-70
Unit
Min Max
t_DPD
Time from DPD entry to DPD exit
150
us
t_DPDX CE# LOW time to exit DPD
10
us
t_PU
Initialization Period (required before normal operations)
150
us
Notes
Rev. B | July 2012
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