IS66WVC4M16ALL Datasheet, PDF (59/67 Pages) Integrated Silicon Solution, Inc – Mixed Mode supports asynchronous write and synchronous read operation

IS66WVC4M16ALL
IS67WVC4M16ALL
Figure 44: Burst WRITE interrupted by Burst WRITE – Fixed Latency Mode
CLK
Address
DQ0-
DQ15
ADV#
CE#
VALID
ADDRESS
t_SP
t_AVH
t_SP t_HD
t_CSP
UB#/LB#
WE#
t_SP t_HD
OE#
t_CEW
WAIT
VALID
ADDRESS
VALID
INPUT
t_CEM (Note 3)
VALID VALID VALID
INPUT INPUT INPUT
VALID
INPUT
t_HD
t_KHTL
Notes:
1. Non-default BCR settings for burst WRITE interrupted by burst WRITE in fixed latency mode:
fixed latency; latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay.
2. Burst interrupt shown on first allowable clock (such as after first data word written).
3. CE# can stay LOW between burst operations, but CE# must not remain LOW longer than tCEM.
Rev. B | July 2012
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