IS66WVC4M16ALL Datasheet, PDF (19/67 Pages) Integrated Silicon Solution, Inc – Mixed Mode supports asynchronous write and synchronous read operation

IS66WVC4M16ALL
IS67WVC4M16ALL
Figure 10: Configuration Register READ
– Synchronous Mode Followed by Data READ
CLK
t_CLK
t_ABA
Address
DQ0-
DQ15
Select
Control
Register²
t_SP t_HD
ADV#
t_SP
t_HD
t_CSP
t_ABA
CE#
t_SP
UB#/LB#
WE#
t_{SP tHD}
OE#
t_CEW
HiZ
WAIT
t_HD
CRE⁴
VALID
ADDRESS
t_ACLK t_KOH t_SP t_HD
CR
valid
t_ACLK t_KOH
VALID VALID VALID VALID
OUTPUTOUTPUTOUTPUTOUTPUT
t_CBPH3
t_CEM
t_HD
t_KTHL
t_CEW
t_BOE
t_KHTL
t_OHZ
t_HZ
t_SP
Notes:
1. Non-default BCR settings for configuration register READ in synchronous mode, followed by READ ARRAY
operation: Latency code three (four clocks); WAIT active LOW; WAIT asserted during delay.
2. A[19:18] = 00b to read RCR, 10b to read BCR, to 01b to read DIDR.
3. CE# must remain LOW to complete a burst-of-one READ. WAIT must be monitored additional WAIT
cycles caused by refresh collisions require a corresponding number of additional CE# LOW cycles.
4. CRE must be HIGH to access registers.
Rev. B | July 2012
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