X28HC256_15 Datasheet, PDF (9/19 Pages) Intersil Corporation – 256k, 32k x 8-Bit, 5V, Byte Alterable EEPROM

DATA Polling Timing Diagram (Note 16)
X28HC256
ADDRESS
A_n
A_n
A_n
CE
WE
t_OEH
OE
I/O₇
D_IN = X
D_OUT = X
t_WC
FIGURE 6. DATA POLLING TIMING DIAGRAM
Toggle Bit Timing Diagram (Note 16)
CE
t_OES
t_DW
D_OUT = X
WE
t_OEH
OE
HIGH Z
I/O₆
(Note 17)
t_WC
FIGURE 7. TOGGLE BIT TIMING DIAGRAM
NOTES:
16. Polling operations are by definition read cycles and are therefore subject to read cycle timings.
17. I/O₆ beginning and ending state will vary, depending upon actual t_WC.
(Note 17)
t_OES
t_DW
Submit Document Feedback
9
FN8108.5
August 27, 2015