X28HC256_15 Datasheet, PDF (12/19 Pages) Intersil Corporation – 256k, 32k x 8-Bit, 5V, Byte Alterable EEPROM

X28HC256
LAST
WE ^WRITE
CE
OE
I/O₆
V_OH
(Note 18)
V_OL
NOTE:
18. I/O6 Beginning and ending state of I/O6 will vary.
HIGH Z
(Note 18)
X28C512, X28C513
READY
FIGURE 10. TOGGLE BIT BUS SEQUENCE
¬
Software Data Protection
LAST WRITE
YES
LOAD ACCUM
FROM ADDR n
COMPARE
ACCUM WITH
ADDR n
COMPARE
NO
OK?
YES
The X28HC256 offers a software controlled data protection
feature. The X28HC256 is shipped from Intersil with the software
data protection NOT ENABLED; that is, the device will be in the
standard operating mode. In this mode data should be protected
during power-up/down operations through the use of external
circuits. The host would then have open read and write access of
the device once V_CC was stable.
The X28HC256 can be automatically protected during power-up
and power-down (without the need for external circuits) by
employing the software data protection feature. The internal
software data protection circuit is enabled after the first write
operation, utilizing the software algorithm. This circuit is
nonvolatile, and will remain set for the life of the device unless
the reset command is issued.
Once the software protection is enabled, the X28HC256 is also
protected from inadvertent and accidental writes in the powered
up state. That is, the software algorithm must be issued prior to
writing additional data to the device.
X28C256
READY
FIGURE 11. TOGGLE BIT SOFTWARE FLOW
Software Algorithm
Selecting the software data protection mode requires the host
system to precede data write operations by a series of three
write operations to three specific addresses. Refer to
Figures 12 and 13 on page 13 for the sequence. The 3 byte
sequence opens the page write window, enabling the host to
write from one to 128 bytes of data. Once the page load cycle
has been completed, the device will automatically be returned
to the data protected state.
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FN8108.5
August 27, 2015