X28HC256_15 Datasheet, PDF (8/19 Pages) Intersil Corporation – 256k, 32k x 8-Bit, 5V, Byte Alterable EEPROM

Page Write Cycle
X28HC256
OE
(Note 13)
CE
WE
t_WP
t_BLC
t_WPH
ADDRESS
(Note 14, 15)
I/O
LAST BYTE
BYTE 0
BYTE 1
BYTE 2
BYTE n
BYTE n + 1
BYTE n + 2
t_WC
FIGURE 6. PAGE WRITE CYCLE
NOTES:
13. Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE HIGH to fetch data
from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively performing a polling operation.
14. The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform to either the CE
or WE controlled write cycle timing.
15. For each successive write within the page write operation, A7 to A15 should be the same or writes to an unknown address could occur.
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FN8108.5
August 27, 2015