X28HC256_15 Datasheet, PDF (10/19 Pages) Intersil Corporation – 256k, 32k x 8-Bit, 5V, Byte Alterable EEPROM

X28HC256
Device Operation
Read
Read operations are initiated by both OE and CE LOW. The read
operation is terminated by either CE or OE returning HIGH. This
two line control architecture eliminates bus contention in a
system environment. The data bus will be in a high impedance
state when either OE or CE is HIGH.
Write
Write operations are initiated when both CE and WE are LOW and
OE is HIGH. The X28HC256 supports both a CE and WE controlled
write cycle. That is, the address is latched by the falling edge of
either CE or WE, whichever occurs last. Similarly, the data is
latched internally by the rising edge of either CE or WE, whichever
occurs first. A byte write operation, once initiated, will
automatically continue to completion, typically within 3ms.
Page Write Operation
The page write feature of the X28HC256 allows the entire
memory to be written in typically 0.8 seconds. The page write
allows up to 128 bytes of data to be consecutively written to the
X28HC256, prior to the commencement of the internal
programming cycle. The host can fetch data from another device
within the system during a page write operation (change the
source address), but the page address (A₇ through A₁₄) for each
subsequent valid write cycle to the part during this operation
must be the same as the initial page address.
The page write mode can be initiated during any write operation.
Following the initial byte write cycle, the host can write an
additional one to 127 bytes in the same manner as the first byte
was written. Each successive byte load cycle, started by the WE
high-to-low transition, must begin within 100µs of the falling
edge of the preceding WE. If a subsequent WE high-to-low
transition is not detected within 100µs, the internal automatic
programming cycle will commence. There is no page write
window limitation. Effectively the page write window is infinitely
wide, so long as the host continues to access the device within
the byte load cycle time of 100µs.
Write Operation Status Bits
The X28HC256 provides the user two write operation status bits.
These can be used to optimize a system write cycle time. The
status bits are mapped onto the I/O bus as shown in Figure 7.
DATA Polling (I/O₇)
The X28HC256 features DATA polling as a method to indicate to the
host system that the byte write or page write cycle has completed.
DATA polling allows a simple bit test operation to determine the
status of the X28HC256. This eliminates additional interrupt inputs
or external hardware. During the internal programming cycle, any
attempt to read the last byte written will produce the complement of
that data on I/O₇ (i.e., write data = 0xxx xxxx, read data = 1xxx xxxx).
Once the programming cycle is complete, I/O₇ will reflect true data.
Toggle Bit (I/O₆)
The X28HC256 also provides another method for determining
when the internal write cycle is complete. During the internal
programming cycle I/O₆ will toggle from high-to-low and high-to-
low on subsequent attempts to read the device. When the
internal cycle is complete the toggling will cease and the device
will be accessible for additional read and write operations.
DATA Polling I/O
DATA polling can effectively halve the time for writing to the
X28HC256. The timing diagram in Figure 8 on page 11
illustrates the sequence of events on the bus. The software flow
diagram in Figure 9 on page 11 illustrates one method of
implementing the routine.
The Toggle Bit I/O
The toggle bit can eliminate the chore of saving and fetching the
last address and data in order to implement DATA polling. This
can be especially helpful in an array comprised of multiple
X28HC256 memories that is frequently updated. The timing
diagram in Figure 10 on page 12 illustrates the sequence of
events on the bus. The software flow diagram in Figure 11 on
page 12 illustrates a method for polling the toggle bit.
Hardware Data Protection
The X28HC256 provides two hardware features that protects
nonvolatile data from inadvertent writes.
• Default V_CC Sense — All write functions are inhibited when V_CC
is 3.5V typically.
• Write Inhibit — Holding either OE low, WE high, or CE high will
prevent an inadvertent write cycle during power-up and
power-down, maintaining data integrity.
I/O DP TB 5
4
3
2
1
0
RESERVED
TOGGLE BIT
DATA POLLING
FIGURE 7. STATUS BIT ASSIGNMENT
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FN8108.5
August 27, 2015