X28HC256_15 Datasheet, PDF (13/19 Pages) Intersil Corporation – 256k, 32k x 8-Bit, 5V, Byte Alterable EEPROM

X28HC256
Software Data Protection
V_CC
0V
DATA
ADDRESS
CE
AA
5555
55
2AAA
WE
A0
5555
£t_{BLC MAX}
WRITES
OK
t_WC
BYTE
OR
AGE
(V_CC)
WRITE
PROTECTED
WRITE DATA AA
TO ADDRESS
5555
WRITE DATA 55
TO ADDRESS
2AAA
WRITE DATA A0
TO ADDRESS
5555
WRITE DATA XX
TO ANY
ADDRESS
WRITE LAST
BYTE TO
LAST ADDRESS
AFTER t_WC
RE-ENTERS DATA
PROTECTED STATE
FIGURE 12. TIMING SEQUENCE BYTE OR PAGE WRITE
Regardless of whether the device has previously been protected
or not, once the software data protection algorithm is used and
data has been written, the X28HC256 will automatically disable
further writes unless another command is issued to cancel it. If
no further commands are issued the X28HC256 will be write
protected during power-down and after any subsequent
power-up.
Note: Once initiated, the sequence of write operations should not
be interrupted.
Resetting Software Data
Protection
BYTE/PAGE
LOAD ENABLED
OPTIONAL
BYTE/PAGE
LOAD OPERATION
In the event the user wants to deactivate the software data
protection feature for testing or reprogramming in an EEPROM
programmer, the following six step algorithm will reset the
internal protection circuit. After t_WC, the X28HC256 will be in
standard operating mode.
Note: Once initiated, the sequence of write operations should not
be interrupted.
FIGURE 13. WRITE SEQUENCE FOR SOFTWARE DATA
PROTECTION
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FN8108.5
August 27, 2015