D2-926XX Datasheet, PDF (9/37 Pages) Intersil Corporation – Integrated DSP Digital Sound Processing

D2-926xx
SPI™ Interface Port Timing (Figure 3) T_A = +25°C, CVDD = PLLVDD = 1.8V ±5%, RVDD = PWMVDD = 3.3V ±10%. All grounds at 0.0V.
All voltages referenced to ground.
SYMBOL
DESCRIPTION
MIN
(Note 14)
MAX
(Note 14)
UNIT
SPI MASTER MODE TIMING
t_V
MOSI Valid From Clock Edge
t_S
MISO Set-Up to Clock Edge
t_H
MISO Hold From Clock Edge
t_WI
nCS Minimum Width
8
ns
2
ns
2
ns
3
3 system clocks
+ 2ns
SPI SLAVE MODE TIMING
t_V
MISO Valid From Clock Edge
t_S
MOSI Set-Up to Clock Edge
t_H
MOSI Hold From Clock Edge
t_WI
nCS Minimum Width
8
ns
2
ns
2
ns
3
3 system clocks
+ 2ns
SCK (CPHA = 1, CPOL = 0
SCK (CPHA = 0, CPOL = 0
t_V
t_V
MOSI
t_H
t_S
MISO (CPHA = 0
t_WI
nCS
FIGURE 3. SPI TIMING
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9
FN6787.3
May 17, 2016