D2-926XX Datasheet, PDF (18/37 Pages) Intersil Corporation – Integrated DSP Digital Sound Processing

D2-926xx
Pin Description DAE-3HT (72-Pin) (Continued)
PIN
VOLTAGE DRIVE
NAME
LEVEL STRENGTH
PIN (Note 18) TYPE (V)
(mA)
DESCRIPTION
25 IRQB
In
3.3
Interrupt request Port B, Boot Mode Select. One of 4 IRQ pins. Connects to logic high (3.3V) or to
ground and High/Low logic status establishes boot mode selection upon de-assertion of reset
(nRESET) cycle.
26 IRQC
In
3.3
Interrupt request Port C, Boot Mode Select. One of 4 IRQ pins. Connects to logic high (3.3V) or to
ground and High/Low logic status establishes boot mode selection upon de-assertion of reset
(nRESET) cycle.
27 IRQD
In
3.3
Interrupt request Port D, Boot Mode Select. One of 4 IRQ pins. Connects to logic high (3.3V) or to
ground and High/Low logic status establishes boot mode selection upon de-assertion of reset
(nRESET) cycle.
28 CVDD
P
3.3
Core power, 1.8V
29 CGND
G
3.3
Core ground
30 RGND
G
3.3
Digital pad ring ground. Internally connected to PWMGND.
31 RVDD
P
3.3
32 PROTECT3 In
3.3
33 PROTECT4 In
3.3
34 PROTECT5 In
3.3
35 PROTECT6 I/O
3.3
/nMUTE
36 PROTECT7 In
3.3
/nOVRT
37 PROTECT2 In
3.3
38 RVDD
P
3.3
39 RGND
G
3.3
40 CGND
G
3.3
Digital pad ring power, 3.3V. This 3.3V supply is used for all the digital I/O pad drivers and
receivers. Internally connected to PWMVDD.
4
PWM protection input with hysteresis. (One of 8 protection inputs. Specific function, channel
assignment, and optional GPIO is defined by firmware.)
4
PWM protection input with hysteresis. (One of 8 protection inputs. Specific function, channel
assignment, and optional GPIO is defined by firmware.)
4
PWM protection input with hysteresis. (One of 8 protection inputs. Specific function, channel
assignment, and optional GPIO is defined by firmware.)
4
PWM protection input with hysteresis, or optional mute output. (One of 8 protection inputs.
Specific function, channel assignment, and/or optional GPIO is defined by firmware.)
4
PWM protection input with hysteresis, or optional over-temperature monitor input. (One of 8
protection inputs. Specific function, channel assignment, and/or optional GPIO is defined by
firmware.)
4
PWM protection input with hysteresis. (One of 8 protection inputs. Specific function, channel
assignment, and optional GPIO is defined by firmware.)
Digital pad ring power, 3.3V. This 3.3V supply is used for all the digital I/O pad drivers and
receivers. Internally connected to PWMVDD.
Digital pad ring ground. Internally connected to PWMGND.
Core ground
41 CVDD
P
3.3
Core power, 1.8V
42 PWM11 O
3.3
8 or 16 PWM output pin. (One of 12 PWM output pins. Channel and operation assignment is defined by
firmware.)
43 PWM10 O
3.3
8 or 16 PWM output pin. (One of 12 PWM output pins. Channel and operation assignment is defined by
firmware.)
44 PWM9
O
3.3
8 or 16 PWM output pin. (One of 12 PWM output pins. Channel and operation assignment is defined by
firmware.)
45 PWM8
O
3.3
8 or 16 PWM output pin. (One of 12 PWM output pins. Channel and operation assignment is defined by
firmware.)
46 PWM7
O
3.3
8 or 16 PWM output pin. (One of 12 PWM output pins. Channel and operation assignment is defined by
firmware.)
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FN6787.3
May 17, 2016