D2-926XX Datasheet, PDF (25/37 Pages) Intersil Corporation – Integrated DSP Digital Sound Processing

D2-926xx
S/PDIF Digital Audio Interface
The device families include a S/PDIF Digital receiver and
transmitter.
• The DAE-3 devices (128 pin packaged devices) include an
on-chip multiplexer supporting switching of input from 2
different S/PDIF input pins. Input selection determines which
pin routes to the S/PDIF receiver.
• The DAE-3HT devices (72 pin packaged devices) support one
input pin only and do not use multiplex switching.
All of the devices in the family include a S/PDIF Digital
transmitter.
S/PDIF RECEIVER
The S/PDIF receiver input pins are 3.3V CMOS input level
compatible, requiring external circuitry to condition the serial
input. The receiver contains an input transition detector, digital
PLL clock recovery, and a decoder to separate audio, channel
status, and user data. Only the first 24-Channel status bits are
supported. The receiver constantly monitors the incoming data
stream to detect the IEC61937-1 packet headers, and if found,
captures the Pc and Pd data words into registers. The receiver
meets the jitter tolerance specified in IEC60958-4.
S/PDIF is typically used for receiving compressed
(IEC61937-compliant) as well as stereo PCM (IEC60958-
compliant) audio data. This interface also supports receipt of
compressed audio data that is not compliant with the IEC61937
specification, but instead meets the IEC60958 specification.
S/PDIF receive data is routed through the SRC, providing a time
synchronized audio input stream for use within any of the DAE
audio processing channels. Audio may be presented on the
S/PDIF input asynchronous to audio also being presented to the
I²S Serial Digital inputs such that after routing through the SRC,
are synchronous time aligned for internal DAE audio processing.
S/PDIF TRANSMITTER
The transmitter complies with the consumer applications defined
in IEC60958-3. The transmitter supports 24-bit audio data, 24-bit
user data, and 30-bit channel status data. S/PDIF output is linear
PCM only and is non-compressed. Routing of compressed audio
that is presented to the DAE inputs must be decoded by the DAE
and its firmware before the selected channels may be routed to
the S/PDIF outputs.
Audio routing to the S/PDIF transmitter is defined by the signal
flow built by the Audio Canvas III software. That software
supports assigning any of the audio processing channels to the 2
(L/R) channels of the S/PDIF output. Because all timing of the
internal audio processing is synchronous to the internal DSP and
processing channels, the S/PDIF audio output is also
synchronous to that internal timing.
ADC input (DAE-3 Devices Only)
The DAE-3 devices contains a high-performance Analog-to-Digital
Converter (ADC) that connects to input analog sources with a
minimum of interface circuitry. The ADC is included in the DAE-3
devices only. It is not supported in the DAE-3HT devices.
At a bandwidth of 20kHz at nominal voltage and temperature,
the ADC input of the DAE-3 provides a typical THD+N
(unweighted) value of -81dB and a typical SNR/Dynamic Range
of 83dB. These typical performances are based on a 1.0V_P-P 1
kHz sine wave input reference level, using a representative
system-level amplifier environment processing digital audio data
and producing PWM amplifier outputs.
Analog performance is affected by factors that include PCB
layout, shielding and routing of analog traces, additional
components within the analog input path, and proper power
supply isolation techniques.
The ADC master clock is supplied from the low jitter PLL of the
D2-926xx. The ADC operates synchronous to the DSP processing
which minimizes noise pickup.
PWM Audio Amplifier Outputs
The DAE-3 family devices include an integrated 12-channel PWM
engine. Each engine is independently programmable for timing,
output pin assignment and audio processing path source.
PWM operation is defined by firmware. The Audio Canvas III
design tool provides the selection for audio channel assignment
routing, protection enabling, timing, and PWM output pin
mapping, then uses these selections to build the firmware that
controls the PWM outputs. Some features such as dead-band
timing are also adjustable in real-time through the control
interface.
Programmability enable use of multiple PWM output topologies,
which supporting system designs of a broad range of output
stages. Output topologies include integrated power stages, or
discrete implementations using N+N or P+N for half-bridge,
full-bridge or bridged-tied-load power stages. The PWM outputs
may be used for powered outputs, and may also be used for
driving line-level or headphone outputs.
The 12 PWM channels are mapped to the PWM output pins by
firmware register assignment. Both DAE-3 and DAE-3HT include
12 PWM engines, and their available pins are:
• DAE-3 - 18 assignable and mappable pins
• DAE-3HT- 12 assignable and mappable pins
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FN6787.3
May 17, 2016