D2-926XX Datasheet, PDF (7/37 Pages) Intersil Corporation – Integrated DSP Digital Sound Processing

D2-926xx
Electrical Specifications T_A = +25°C, CVDD = PLLVDD = 1.8V ±5%, RVDD = PWMVDD = 3.3V ±10%. All grounds at 0.0V. All voltages
referenced to ground. PLL at 294.912MHz, OSC at 24.576MHz, core running at 147.456MHz with typical audio data traffic. Minimum supply currents are
measured in full power down configuration. (Continued)
SYMBOL
PARAMETER
TEST
MIN
MAX
CONDITIONS
(Note 14)
TYP
(Note 14) UNIT
THD+N
-
-80
-
dB
Gain Mismatch
-
0.1
-
dB
Crosstalk
-
-80
-
dB
Power Supply Rejection
-
-70
-
dB
NOTES:
11. All input pins except XTALI.
12. Input leakage applies to all pins except XTALO.
13. Power-down is with device in reset and clocks stopped.
14. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
15. Analog performance is system-design dependent and is affected by factors that include PCB layout, shielding and routing of analog traces, additional
components within the analog input path, and power supply isolation.
Serial Audio Interface Port Timing (Figure 1) T_A = +25°C, CVDD = PLLVDD = 1.8V ±5%, RVDD = PWMVDD = 3.3V ±10%. All
grounds at 0.0V. All voltages referenced to ground.
SYMBOL
DESCRIPTION
MIN
(Note 14)
MAX
TYP
(Note 14)
UNIT
tc_SCLK
tw_SCLK
ts_LRCLK
th_LRCLK
ts_SDI
th_SDI
t_dSDO
SCKRx Frequency - SCKR0, SCKR1
SCKRx Pulse Width (High and Low) - SCKR0, SCKR1
LRCKRx Set-Up to SCLK Rising - LRCKR0, LRCKR1
LRCKRx Hold from SCLK Rising - LRCKR0, LRCKR1
SDINx Set-Up to SCLK Rising - SDIN0, SDIN1
SDINx Hold from SCLK Rising - SDIN0, SDIN1
SDOUTx Delay from SCLK Falling
12.5
MHz
40
ns
20
ns
20
ns
20
ns
20
ns
20
ns
t_cSCLK
t_wSCLK
SCKRx
t_hLRCLK
LRCLKRx
t_sLRCLK
t_wSCLK
t_sSDI
SDINx
t_dSDO
t_hSDI
SDOUTx
FIGURE 1. SERIAL AUDIO INTERFACE PORT TIMING
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FN6787.3
May 17, 2016