D2-926XX Datasheet, PDF (28/37 Pages) Intersil Corporation – Integrated DSP Digital Sound Processing

D2-926xx
Reading and Writing Control Registers
DAE control is provided through the I²C port, using registers and
memory spaces that are defined within the firmware. After
booting and initialization, this control port provides continuous
read and write access for control and monitoring of the amplifier
system. Register addresses are dynamic based on the audio path
signal flow and hardware options selected for the particular
project. Address locations are generated for each system through
a header file from the Audio Canvas III design tool that maps the
address location to each parameter of the system.
The I²C port is used for reading and writing the control data. The
highest-order byte of the register address (bits 23:16) determines
the internal address space used for control read or write access,
and the remaining 16 bits (bits 15:0) describe the actual address
within that space.
All reads or writes to registers (shown in Figures 7 and 8) begin
with a Start Condition, followed by the Device Address byte, three
Register Address bytes, three Data bytes and a Stop Condition.
Register writes through the I²C interface are initiated by setting
the read/write bit that is within the device address byte. The
device write function as, shown in Figure 7, executes the
following 9 steps as the I²C bus master:
1. I²C START command
2. Transmit device I²C address with W
3. Transmit mode byte
4. Transmit upper memory address byte
5. Transmit lower memory address byte
6. Transmit data upper byte
7. Transmit data middle byte
8. Transmit data lower byte
9. I²C STOP command
All reads to registers require two steps. First, the master must
send a dummy write which consist of sending a Start, followed by
the device address with the write bit set, and three register
address bytes. Next, the master must send a repeated Start,
following with the device address with the read/write bit set to
read, and then read the next three data bytes. The master must
Acknowledge (ACK) the first two read bytes and send a Not
Acknowledge (NACK) on the third byte received and a Stop
condition to complete the transaction. The device's control
interface acknowledges each byte by pulling SDA low on the bit
immediately following each write byte. The device read function,
as shown in Figure 8, executes the following 11 steps as the I²C
bus master:
1. I²C START command
2. Transmit device I²C address with W
3. Transmit mode byte
4. Transmit upper memory address byte
5. Transmit lower memory address byte
6. Repeat START command
7. Transmit device I²C address with R
8. Receive data upper byte
9. Receive data middle byte
10. Receive data lower byte
11. I²C STOP command or NACK
DEVICE-ADDR
ACK
REGISTER [23:16]
ACK
REGISTER [15:8]
ACK
REGISTER [7:0]
START
Write Sequence
R/W
REGISTER [7:0]
ACK
DATA [23:16]
ACK
DATA [15:8]
ACK
DATA [7:0]
ACK
DEVICE-ADDR
FIGURE 7. I²C WRITE SEQUENCE OPERATION
ACK
REGISTER [23:16]
Step 1
ACK
REGISTER [15:8]
ACK
REGISTER [7:0]
ACK
START
Read Sequence
ACK
R/W
DEVICE-ADDR
ACK
DATA [23:16]
MASTER
ACK
DATA [15:8]
MASTER
ACK
REPEAT
START
DATA [7:0]
REPEAT
START
R/W
Step 2
FIGURE 8. I²C READ SEQUENCE OPERATION
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STOP
NACK
STOP
FN6787.3
May 17, 2016