D2-926XX Datasheet, PDF (8/37 Pages) Intersil Corporation – Integrated DSP Digital Sound Processing

D2-926xx
Two-Wire (I²C) Interface Port Timing (Figure 2) T_A = +25°C, CVDD = PLLVDD = 1.8V ±5%, RVDD = PWMVDD = 3.3V ±10%. All
grounds at 0.0V. All voltages referenced to ground.
SYMBOL
DESCRIPTION
MIN
(Note 14)
MAX
(Note 14)
UNIT
f_SCL
SCL Frequency
t_buf
Bus Free Time Between Transmissions
tw_lowSCLx
SCL Clock Low
tw_highSCLx
SCL Clock High
ts_STA
Set-Up Time For a (Repeated) Start
th_STA
Start Condition Hold Time
th_SDAx
SDA Hold From SCL Falling (Note 16)
ts_SDAx
SDA Set-Up Time to SCL Rising
td_SDAx
SDA Output Delay Time From SCL Falling
t_r
Rise Time of Both SDA and SCL
t_f
Fall Time of Both SDA and SCL
ts_STO
Set-Up Time For a Stop Condition
NOTE:
16. Data must be held sufficient time to bridge the 300ns transition time of SCL.
100
kHz
4.7
µs
4.7
µs
4.0
µs
4.7
µs
4.0
µs
0
µs
250
ns
3.5
µs
1
µs
300
ns
4.7
µs
t_whighSCLx
t_wlowSCLx
SCLx
t_sSTA
SDAx (INPUT)
SDAx (OUTPUT)
t_R
t_F
tsSDAx
t_hSTAx
t_hSDAx
t_sSTO
t_dSDAx
FIGURE 2. I²C INTERFACE TIMING
t_BUF
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8
FN6787.3
May 17, 2016