D2-7XX83_14 Datasheet, PDF (9/33 Pages) Intersil Corporation – Intelligent Digital Amplifier and Sound Processor

D2-7xx83
Two-Wire (I²C) Interface Port Timing (Figure 2) T_A = +25°C, CVDD = PLLVDD = 1.8V ±5%, RVDD = PWMVDD = 3.3V ±10%.
All grounds at 0.0V. All voltages referenced to ground.
SYMBOL
DESCRIPTION
MIN
(Note 10)
TYPICAL
MAX
(Note 10)
UNIT
f_SCL
SCL Frequency
t_buf
Bus Free Time Between Transmissions
tw_lowSCLx
SCL Clock Low
tw_highSCLx
SCL Clock High
ts_STA
Setup Time For a (Repeated) Start
th_STA
Start Condition Hold Time
th_SDAx
SDA Hold From SCL Falling (Note 12)
ts_SDAx
SDA Setup Time to SCL Rising
td_SDAx
SDA Output Delay Time From SCL Falling (Note 13)
t_r
Rise Time of Both SDA and SCL (Note 13)
t_f
Fall Time of Both SDA and SCL (Note 13)
ts_STO
Setup Time For a Stop Condition
NOTE:
12. Data is clocked in as valid on next XTALI rising edge after SCL goes low.
13. Limits established by characterization and not production tested.
100
kHz
4.7
µs
4.7
µs
4.0
µs
4.7
µs
4.0
µs
1
µs
250
ns
3.5
µs
1
µs
300
ns
4.7
µs
t_whighSCLx
t_wlowSCLx
SCLx
t_sSTA
SDAx (INPUT)
SDAx (OUTPUT)
t_R
t_F
tsSDAx
t_hSTAx
t_hSDAx
t_sSTO
t_dSDAx
FIGURE 2. I²C INTERFACE TIMING
t_BUF
9
FN7838.2
September 29, 2011