D2-7XX83_14 Datasheet, PDF (10/33 Pages) Intersil Corporation – Intelligent Digital Amplifier and Sound Processor

D2-7xx83
SPI™ Interface Port Timing (Figure 3) TA = +25°C, CVDD = PLLVDD = 1.8V ±5%, RVDD = PWMVDD = 3.3V ±10%. All grounds at
0.0V. All voltages referenced to ground.
SYMBOL
DESCRIPTION
MIN
(Note 10)
MAX
(Note 10)
UNIT
SPI MASTER MODE TIMING
t_V
MOSI Valid From Clock Edge
t_S
MISO Setup to Clock Edge
t_H
MISO Hold From Clock Edge
t_WI
nSS Minimum Width
SPI SLAVE MODE TIMING
-
8
ns
10
-
ns
1 system clock + 2ns
3 system clocks + 2ns
t_V
MISO Valid From Clock Edge
t_S
MOSI Setup to Clock Edge
t_H
MOSI Hold From Clock Edge
t_WI
nSS Minimum Width
3 system clocks + 2ns
10
-
ns
1 system clock + 2ns
3 system clocks + 2ns
SCK (CPHA = 1, CPOL = 0
SCK (CPHA = 0, CPOL = 0
t_V
t_V
MOSI
t_H
t_S
MISO (CPHA = 0
t_WI
nSS
FIGURE 3. SPI TIMING
10
FN7838.2
September 29, 2011