D2-7XX83_14 Datasheet, PDF (12/33 Pages) Intersil Corporation – Intelligent Digital Amplifier and Sound Processor

D2-7xx83
Pin Descriptions
PIN
NAME
PIN (Note 14) TYPE
VOLTAGE
LEVEL
(V)
1
SC20
I/O
3.3
2
SRD2
I/O
3.3
3
SC21
I/O
3.3
4
SCK2
I/O
3.3
5
STD2
I/O
3.3
6
SC22
I/O
3.3
7
MCLK
O
3.3
8
SCK3
I/O
3.3
9
STD3
I/O
3.3
10
SC32
I/O
3.3
11
SC30
I/O
3.3
12 SC31
I/O
3.3
13 SRD3
I/O
3.3
14
STD0
I/O
3.3
15 SCK0
I/O
3.3
16 CVDD
P
3.3
17 CVDD
P
3.3
18 CGND
P
3.3
19 CGND
P
3.3
20 RGND
P
3.3
21 RVDD
P
3.3
22 SRD0
I/O
3.3
23
SC00
I/O
3.3
24
SC01
I/O
3.3
25
SC02
I/O
3.3
26
SCK
I/O
3.3
27
TIO1
I/O
3.3
28
MISO
I/O
3.3
29
MOSI
I/O
3.3
30 GPIO7
I/O
3.3
31 GPIO3
I/O
3.3
32 GPIO2
I/O
3.3
33 GPIO4
I/O
3.3
DRIVE
STRENGTH
(mA)
8
4
8
8
8
4
16
8
8
8
8
8
4
8
8
DESCRIPTION
Serial Audio Interface 2, I²S0 SCLK
Serial Audio Interface 2, I²S0 SDIN
Serial Audio Interface 2, I²S0 LRCK
Serial Audio Interface 2, I²S1 SCLK
Serial Audio Interface 2, I²S1 SDIN
Serial Audio Interface 2, I²S1 LRCK
I²S Serial Audio Master Clock output for external ADC/DAC components, drives low on reset
and is enabled by firmware assignment.
Serial Audio Interface 3, I²S3 SCLK
Serial Audio Interface 3, I²S3 SDIN
Serial Audio Interface 3, I²S3 LRCK
Serial Audio Interface 3, I²S2 SCLK
Serial Audio Interface 3, I²S2 LRCK
Serial Audio Interface 3, I²S2 SDIN
Serial Audio Interface 0, I²S SDAT0
Serial Audio Interface 0, I²S LRCK0
Core power, 1.8V
Core power, 1.8V
Core ground
Core ground
Digital pad ring ground. Internally connected to PWMGND.
Digital pad ring power, 3.3V. This 3.3V supply is used for all the digital I/O pad drivers and
receivers, except for the analog pads. Internally connected to PWMVDD.
4
Serial Audio Interface 0, SDIO, Defaults to input, and may be configured as GPIO by firmware.
8
Serial Audio Interface 0, SDIO, Defaults to input, and may be configured as GPIO by firmware.
8
Serial Audio Interface 0, I²S SDAT1
8
Serial Audio Interface 0, I²S LRCK1
4
SPI clock I/O with hysteresis input.
16
Timer I/O port 1. Operation and assignment is controlled by firmware. Leave unconnected
when not in use.
4
SPI master input, slave output data signal.
4
SPI master output, slave input data signal.
16
General purpose I/O Bidirectional GPIO port. (One of 8 GPIO. Resets to input port. Operation
and assignment is defined by product application's firmware.)
16
General purpose I/O Bidirectional GPIO port. (One of 8 GPIO. Resets to input port. Operation
and assignment is defined by product application's firmware.)
16
General purpose I/O Bidirectional GPIO port. (One of 8 GPIO. Resets to input port. Operation
and assignment is defined by product application's firmware.)
16
General purpose I/O Bidirectional GPIO port. (One of 8 GPIO. Resets to input port. Operation
and assignment is defined by product application's firmware.)
12
FN7838.2
September 29, 2011