D2-7XX83_14 Datasheet, PDF (25/33 Pages) Intersil Corporation – Intelligent Digital Amplifier and Sound Processor

HD AUDIO SYSTEM TOPOLOGY
D2-7xx83
Front L/R
DAC
NID 02
Front L/R
Mixer
(Gain Control)
NID 06
Front L/R
Pin Complex
(Mute Control)
NID 0A
HDA Link
Interface
Center / LFE
DAC
NID 03
Surround L/R
DAC
NID 04
Center / LFE
Mixer
(Gain Control)
NID 07
Surround L/R
Mixer
(Gain Control)
NID 08
Center / LFE
Pin Complex
(Mute Control)
NID 0B
Surround L/R
Pin Complex
(Mute Control)
NID 0C
Side Surr L/R
DAC
NID 05
Side Surr L/R
Mixer
(Gain Control)
NID 09
Side Surr L/R
Pin Complex
(Mute Control)
NID 0D
FIGURE 9. HD AUDIO SYSTEM TOPOLOGY
Sample Rate Converters (SRC)
D2-7xx83 family ICs support internal asynchronous sample rate
conversion to align input audio streams to a single rate
compatible with the DSP processing rate and PWM switch rate.
D2-7xx83 device family has 4 independent rate estimators,
allowing up to 4 asynchronous stereo inputs (8 channels) to be
sample rate converted and processed simultaneously. The
sample rate converter has a measured SNR that exceeds 140dB
and a THD+N that exceeds -125dB.
DSP
The majority of the D2-7xx83 audio processing functions as well
as system control occur within the DSP core. The core is a 24-bit
fixed-point Digital Signal Processor, tightly integrated with its
own DMA, interrupt control, memory, and control interfaces.
Software configurable processing blocks and signal routings are
implemented within the DSP, allowing a wide range of
functionality and system implementations through the
programmed definitions that are read into memory upon device
initialization. Signal flows through the device are buffered and
processed through hardware specific-function blocks (such as
the Sample Rate Converter) and allow considerable overall signal
processing capability through interface to the DSP.
Clocks And PLL
The clock generation contains a low jitter PLL critical for low
noise PWM output and a precise master clock source for the
ADC, sample rate conversion, and the audio data paths. The
serial audio interfaces can function as either a master or a slave.
The PLL block contains the following components:
• Low noise crystal oscillator
• Low jitter PLL clock multiplier
• Power on reset generator
• Brown out detectors on the CVDD and RVDD supplies
• System reset generation logic
• Clock generators for the DSP, S/PDIF transmitter, ADC, and
MCLK output pin
The PLL block is completely managed by the system firmware.
The system clock is provided by the crystal oscillator block, using
either a fundamental mode crystal or a clock input to the XTALI
pin. If the clock input is used, it must be a 1.8V signal level. The
input signal on the XTALI pin is analog buffered and driven onto
the OSCOUT pin for use in driving the XTALI input of other
D2-7xx83 controllers.
The PLL uses the signal on the XTALI pin as the reference clock.
The reference clock frequency is multiplied by an integer
multiple of 4 to 15 to get the PLL output clock. The PLL output is
used to time the PWM outputs and to generate the DSP clock.
During system start-up, before the PLL has been configured and
locked, the PLL is bypassed and the system operates at XTALI
speed.
25
FN7838.2
September 29, 2011