D2-7XX83_14 Datasheet, PDF (20/33 Pages) Intersil Corporation – Intelligent Digital Amplifier and Sound Processor

D2-7xx83
S/PDIF RECEIVER
The D2-7xx83 contains two input pins internally multiplexed into
one IEC60958 compliant S/PDIF Digital receiver. The receiver
input pins are 3.3V CMOS input level compatible, requiring
external circuitry to condition the serial input. The receiver
contains an input transition detector, digital PLL clock recovery,
and a decoder to separate audio, channel status, and user data.
Only the first 24-Channel status bits are supported. The receiver
constantly monitors the incoming data stream to detect the
IEC61937-1 packet headers, and if found, captures the Pc and
Pd data words into registers. The receiver meets the jitter
tolerance specified in IEC60958-4.
S/PDIF is a commonly used interface for receiving compressed
(IEC61937-compliant) and stereo PCM (IEC60958-compliant)
audio data. This interface also supports receipt of compressed
audio data that is not compliant with the IEC61937 specification,
but instead meets the IEC60958 specification.
ADC INPUT
The D2-7xx83 contains a high-performance Analog-to-Digital
Converter (ADC) that connects to input analog sources with a
minimum of interface circuitry. At a bandwidth of 20kHz at
nominal voltage and temperature, the ADC input of the DAE-6
provides a typical THD+N (unweighted) value of -81dB and an
SNR/Dynamic Range of 94dB.
The ADC master clock can be supplied from either the low jitter
PLL of the D2-7xx83, or from the HD Audio interface. When the
PLL provides the ADC master clock, the ADC operates
synchronous to the DSP processing, which minimizes noise
pickup. When operated from the HD Audio clock system, the ADC
decimator output is synchronous to the HDA frame rate,
eliminating the need for sample rate conversion to the HDA
frame rate. Figure 6 shows the ADC decimator frequency
response over full bandwidth and passband, and Figure 7 shows
the ADC performance with full scale input processed through the
SRC to a 48kHz sample rate.
0
50
100
150
0
24 BITS
SPEC
0.020
0.015
24 BITS
SPEC
0.010
0.005
0
-0.005
-0.010
-0.015
0.5
1.0
1.5
2.0
2.5
3.0
FREQUENCY (Hz)
x10⁶
-0.020
0
0.5
1.0
1.5
2.0
2.5
3.0
FREQUENCY (Hz)
x10⁴
FIGURE 6. ADC DECIMATOR FREQUENCY RESPONSE (256 TAPS DECIMATE BY 32)
0
fs = 6.144MHz
-20
Ch0 INPUT = 1kHz @ 1V_P-P
THD + N = -81dB SNR = 94dB
-40
-60
-80
-100
-120
-140
0
5k
10k
15k
20k
FREQUENCY (Hz)
FIGURE 7. ADC PERFORMANCE AT FULL SCALE INPUT
20
FN7838.2
September 29, 2011