D2-7XX83_14 Datasheet, PDF (6/33 Pages) Intersil Corporation – Intelligent Digital Amplifier and Sound Processor

D2-7xx83
Absolute Maximum Ratings (Note 6)
Supply Voltage
RVDD, PWMVDD, ADCVDD . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 4.0V
CVDD, PLLVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.4V
Input Voltage
Any Input but XTALI . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to RVDD +0.3V
XTALI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to PLLVDD +0.3V
Input Current, Any Pin but Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . ±10mA
Thermal Information
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
128 Ld LQFP Package (Notes 4, 5) . . . . . .
40
6.5
Maximum Storage Temperature. . . . . . . . . . . . . . . . . . . . -55°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -10°C to +85°C
Digital I/O Supply Voltage, PWMVDD . . . . . . . . . . . . . . . . . . . . . . . . . . .3.3V
Core Supply Voltage, CVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.8V
Analog Supply Voltage, PLLVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.8V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. θ_JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
5. For θ_JC, the “case temp” location is taken at the package top center.
6. Absolute Maximum parameters are not tested in production.
Electrical Specifications T_A = +25°C, CVDD = PLLVDD = 1.8V ±5%, RVDD = PWMVDD = 3.3V ±10%. All grounds at 0.0V. All
voltages referenced to ground. PLL at 294.912MHz, OSC at 24.576MHz, core running at 147.456MHz with typical audio data traffic. Minimum
supply currents are measured in full power down configuration.
SYMBOL
PARAMETER
TEST
MIN
MAX
CONDITIONS
(Note 10)
TYP
(Note 10) UNIT
V_IH Digital Input High Logic Level (Note 7)
RVDD = 3.3V
2.0
-
(Scales with
RVDD)
-
V
V_IL Digital Input Low Logic Level (Note 7)
RVDD = 3.3V
-
-
0.8
V
(Scales with
RVDD)
V_OH High Level Output Drive Voltage
(I_OUT at - Pin Drive Strength Current, see “Pin Descriptions” on
page 12)
RVDD - 0.4
-
-
V
V_OL Low Level Output Drive Voltage
(I_OUT at + Pin Drive Strength Current, see “Pin Descriptions” on
page 12)
-
-
0.4
V
VIHX High Level Input Drive Voltage XTALI Pin
0.7
-
PLLVDD
V
VILX Low Level Input Drive Voltage XTALI Pin
-
-
0.3
V
I_IN
C_IN
VOHO
Input Leakage Current (Note 8)
Input Capacitance
High Level Output Drive Voltage OSCOUT Pin
-
-
-
9
PLLVDD - 0.3
-
±10
µA
-
pF
-
V
VOLO Low Level Output Drive Voltage OSCOUT Pin
-
-
0.3
V
C_OUT
t_RST
R_VDD/
PWM_VDD
Output Capacitance
nRESET Pulse Width
Typical Digital and PWM I/O Pad Ring Supply
(Voltage)
(Current, Active)
-
9
-
pF
-
10
-
ns
3.0
3.3
3.6
V
-
15
-
mA
(Current, Power-down)
-
<1
-
mA
CVDD Typical Core Supply
(Voltage)
1.7
1.8
1.9
V
(Current, Active)
-
450
-
mA
PLLVDD Typical PLL Analog Supply
(Current, Power-down)
(Voltage)
-
15
-
mA
1.7
1.8
1.9
V
(Current, Active)
-
25
-
mA
(Current, Power-down)
-
10
-
mA
6
FN7838.2
September 29, 2011