X9251_14 Datasheet, PDF (8/21 Pages) Intersil Corporation – Single Supply/Low Power/256-Tap/SPI Bus, Quad Digitally-Controlled Potentiometer

CS
SCK
SI
X9251
0 1 0 10
ID3 ID2 ID1 ID0 0
DEVICE ID
0
0 ^{A1 A0} I3 I2 I1 I0 RB RA P1 P0
INTERNAL
ADDRESS
INSTRUCTION REGISTER DCP/WCR
OPCODE
ADDRESS ADDRESS
FIGURE 3. TWO-BYTE INSTRUCTION SEQUENCE
CS
SCK
SI
0 1 0 1 00
ID3 ID2 ID1 ID0 _{0 0 A1 A0}
I3 I2 I1 I0 RB RA ^P1 P0
D7 D6 D5 D4 D3 D2 D1 D0
DEVICE ID
INTERNAL
ADDRESS
INSTRUCTION REGISTER DCP/WCR
OPCODE
ADDRESS ADDRESS
DATA FOR WCR[7:0] OR DR[7:0]
FIGURE 4. THREE-BYTE INSTRUCTION SEQUENCE SPI INTERFACE; WRITE CASE
CS
SCK
SI
0 1 0 1 00
ID3 ID2 ID1 ID0 _{0 0} A1 A0
I3 I2 I1 I0 RB RA P1 P0
XXXX XXXX
DON’T CARE
DEVICE ID
INTERNAL
ADDRESS
INSTRUCTION REGISTER DCP/WCR
OPCODE
ADDRESS ADDRESS
S0
D7 D6 D5 D4 D3 D2 D1 D0
WCR[7:0]
OR
DATA REGISTER BIT [7:0]
FIGURE 5. THREE-BYTE INSTRUCTION SEQUENCE SPI INTERFACE, READ CASE
Submit Document Feedback
8
FN8166.6
December 3, 2014