X9251_14 Datasheet, PDF (5/21 Pages) Intersil Corporation – Single Supply/Low Power/256-Tap/SPI Bus, Quad Digitally-Controlled Potentiometer

X9251
One of Four Potentiometers
#: 0, 1, 2, or 3
SERIAL DATA PATH
FROM INTERFACE
CIRCUITRY
R_H
SERIAL
BUS
INPUT
DR#0
DR#1
8
DR#2
8
PARALLEL
BUS
DR#3
INPUT
WIPER
COUNTER
---
DCP
CORE
R_W
DECODE
COUNTER
REGISTER
(WCR#)
INC/DEC
LOGIC
IF WCR = 00[H] then R_W is closest to R_L
IF WCR = FF[H] then R_W is closest to R_H
UP/DN _UP/DN
MODIFIED SCK
CLK
R_L
FIGURE 2. DETAILED POTENTIOMETER BLOCK DIAGRAM
Power-Up and Down Recommendations
There are no restrictions on the power-up or power-down
conditions of V_CC and the voltages applied to the potentiometer
pins provided that V_CC is always more positive than or equal to
V_H, V_L, and V_W (i.e., V_CC  V_H, V_L, V_W). The V_CC ramp rate
specification is always in effect.
Wiper Counter Register (WCR)
The X9251 contains four Wiper Counter Registers, one for each
potentiometer. The Wiper Counter Register can be envisioned as
a 8-bit parallel and serial load counter with its outputs decoded
to select one of 256 wiper positions along its resistor array. The
contents of the WCR can be altered in four ways: it may be
written directly by the host via the Write Wiper Counter Register
instruction (serial load); it may be written indirectly by
transferring the contents of one of four associated data registers
via the XFR Data Register instruction (parallel load); it can be
modified one step at a time by the Increment/Decrement
instruction (see “Instruction Format” on page 10 for more
details). Finally, it is loaded with the contents of its Data Register
zero (DR#0) upon power-up (see Figure 2).
The wiper counter register is a volatile register; that is, its
contents are lost when the X9251 is powered down. Although the
register is automatically loaded with the value in DR#0 upon
power-up, this may be different from the value present at
power-down. Power-up guidelines are recommended to ensure
proper loadings of the DR#0 value into the WCR#.
Data Registers (DR)
Each of the four DCPs has four 8-bit nonvolatile Data Registers.
These can be read or written directly by the host. Data can also
be transferred between any of the four Data Registers and the
associated Wiper Counter Register. All operations changing data
in one of the Data Registers is a nonvolatile operation and takes
a maximum of 10ms.
If the application does not require storage of multiple settings for
the potentiometer, the Data Registers can be used as regular
memory locations for system parameters or user preference data.
Bits [7:0] are used to store one of the 256 wiper positions or data
(0 ~ 255).
Status Register (SR)
This 1-bit Status Register is used to store the system status.
WIP: Write In Progress status bit, read only.
• WIP = 1, indicates that high-voltage write cycle is in progress.
• WIP = 0, indicates that no high-voltage write cycle is in
progress.
TABLE 1. WIPER COUNTER REGISTER, WCR (8-BIT), WCR[7:0]: USED TO STORE THE CURRENT WIPER POSITION (VOLATILE)
WCR7
WCR6
WCR5
WCR4
WCR3
WCR2
WCR1
WCR0
(MSB)
(LSB)
BIT 7
(MSB)
TABLE 2. DATA REGISTER, DR (8-BIT), DR[7:0]: USED TO STORE WIPER POSITIONS OR DATA (NONVOLATILE)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
(LSB)
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5
FN8166.6
December 3, 2014