X9251_14 Datasheet, PDF (6/21 Pages) Intersil Corporation – Single Supply/Low Power/256-Tap/SPI Bus, Quad Digitally-Controlled Potentiometer

X9251
Serial Interface
The X9251 supports the SPI interface hardware conventions. The
device is accessed via the SI input with data clocked in, on the
rising SCK. CS must be LOW and the HOLD and WP pins must be
HIGH during the entire operation.
The SO and SI pins can be connected together, since they have
three-state outputs. This can help to reduce system pin count.
Identification Byte
The first byte sent to the X9251 from the host, following a CS
going HIGH to LOW, is called the Identification Byte. The most
significant four bits of the Identification Byte are a Device Type
Identifier, ID[3:0]. For the X9251, this is fixed as 0101 (refer to
Table 3).
The least significant four bits of the Identification Byte are the
Slave Address bits, AD[3:0]. For the X9251, A3 is 0, A2 is 0, A1 is
the logic value at the input pin A1, and A0 is the logic value at the
input pin A0. Only the device which Slave Address matches the
incoming bits sent by the master executes the instruction. The A1
and A0 inputs can be actively driven by CMOS input signals or
tied to V_CC or V_SS.
Instruction Byte
The next byte sent to the X9251 contains the instruction and
register pointer information. The four most significant bits are
used to provide the instruction opcode (I[3:0]). The RB and RA
bits point to one of the four Data Registers of each associated
XDCP. The least two significant bits point to one of four Wiper
Counter Registers or DCPs. The format is shown below in Table 4.
ID3
0
(MSB)
DEVICE TYPE IDENTIFIER
ID2
ID1
1
0
TABLE 3. IDENTIFICATION BYTE FORMAT
ID0
A3
1
0
SLAVE ADDRESS
A2
A1
0
Pin A1
Logic Value
A0
Pin A0
Logic Value
(LSB)
I3
(MSB)
INSTRUCTION OPCODE
I2
I1
TABLE 4. INSTRUCTION BYTE FORMAT
REGISTER SELECTION
I0
RB
RA
DCP SELECTION
(WCR SELECTION)
P1
P0
(LSB)
Data Register Selection
REGISTER
RB
RA
DR#0
0
0
DR#1
0
1
DR#2
1
0
DR#3
1
1
#: 0, 1, 2, or 3
INSTRUCTION
Read Wiper Counter Register
Write Wiper Counter Register
Read Data Register
Write Data Register
XFR Data Register to
Wiper Counter Register
TABLE 5. INSTRUCTION SET
INSTRUCTION SET
I3 I2 I1 I0 RB RA P1 P0
OPERATION
1 0 0 1 0 0 1/0 1/0 Read the contents of the Wiper Counter Register
pointed to by P1, P0
1 0 1 0 0 0 1/0 1/0 Write new value to the Wiper Counter Register
pointed to by P1, P0
1 0 1 1 1/0 1/0 1/0 1/0 Read the contents of the Data Register pointed to by
P1, P0 and RB, RA
1 1 0 0 1/0 1/0 1/0 1/0 Write new value to the Data Register pointed to by P1,
P0 and RB, RA
1 1 0 1 1/0 1/0 1/0 1/0 Transfer the contents of the Data Register pointed to by
P1, P0 and RB, RA to its associated Wiper Counter
Register
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FN8166.6
December 3, 2014