X9251_14 Datasheet, PDF (3/21 Pages) Intersil Corporation – Single Supply/Low Power/256-Tap/SPI Bus, Quad Digitally-Controlled Potentiometer

X9251
Ordering Information
PART
PART NUMBER (Notes 2, 3) MARKING
V_CC LIMITS
(V)
POTENTIOMETER
ORGANIZATION
(kΩ)
TEMP RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
X9251US24Z (Note 1) X9251US Z
5 ±10%
50
0 to +70 24 Ld SOIC (300 mil)
M24.3
X9251US24IZ (Note 1) X9251US ZI
-40 to +85 24 Ld SOIC (300 mil)
M24.3
X9251UV24Z
X9251UV Z
0 to +70 24 Ld TSSOP (4.4mm)
M24.173
X9251UV24IZ
X9251UV ZI
-40 to +85 24 Ld TSSOP (4.4mm)
M24.173
X9251US24IZ-2.7 (Note 1) X9251US ZG
2.7 to 5.5
-40 to +85 24 Ld SOIC (300 mil)
M24.3
X9251US24Z-2.7 (Note 1) X9251US ZG
0 to +70 24 Ld SOIC (300 mil)
M24.3
X9251UV24Z-2.7
X9251UV ZF
0 to +70 24 Ld TSSOP (4.4mm)
M24.173
X9251UV24IZ-2.7 (Note 1) X9251UV ZG
-40 to +85 24 Ld TSSOP (4.4mm)
M24.173
NOTES:
1. Add "T1" suffix for tape and reel.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see product information page for X9251. For more information on MSL, please see tech brief TB363
Pin Configuration
X9251
(24 LD SOIC/TSSOP)
TOP VIEW
SO
A0
R_W3
R_H3
R_L3
NC
V_CC
R_L0
R_H0
R_W0
CS
WP
1
24
2
23
3
22
4
21
5
20
6
19
X9251
7
18
8
17
9
16
10
15
11
14
12
13
HOLD
SCK
R_L2
R_H2
R_W2
NC
V_SS
R_W1
R_H1
R_L1
A1
SI
Pin Descriptions
PIN
(SOIC)
SYMBOL
FUNCTION
1
SO Serial Data Output for SPI bus
2
A0 Device Address for SPI bus (see Note 4)
3
R_W3 Wiper Terminal of DCP3
4
R_H3 High Terminal of DCP3
5
R_L3 Low Terminal of DCP3
7
V_CC System Supply Voltage
8
R_L0 Low Terminal of DCP0
9
R_H0 High Terminal of DCP0
10
R_W0 Wiper Terminal of DCP0
11
CS SPI bus. Chip Select active low input
12
WP Hardware Write Protect - active low
13
SI
Serial Data Input for SPI bus
14
A1 Device Address for SPI bus (see Note 4)
15
R_L1 Low Terminal of DCP1
16
R_H1 High Terminal of DCP1
17
R_W1 Wiper Terminal of DCP1
18
V_SS System Ground
20
R_W2 Wiper Terminal of DCP2
21
R_H2 High Terminal of DCP2
22
R_L2 Low Terminal of DCP2
23
SCK Serial Clock for SPI bus
24
HOLD Device select. Pauses the SPI serial bus.
6, 19
NC No Connect
NOTE:
4. A0 and A1 device address pins must be tied to a logic level.
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FN8166.6
December 3, 2014