X9251_14 Datasheet, PDF (15/21 Pages) Intersil Corporation – Single Supply/Low Power/256-Tap/SPI Bus, Quad Digitally-Controlled Potentiometer

Symbol Table
WAVEFORM
INPUTS
Must be
steady
May change
from Low to
High
May change
from High to
Low
Don’t Care:
Changes
Allowed
N/A
OUTPUTS
Will be
steady
Will change
from Low to
High
Will change
from High to
Low
Changing:
State Not
Known
Center Line
is High
Impedance
Timing Diagrams
Input Timing
X9251
CS
SCK
SI
SO
t_LEAD
t_SU
t_H
t_WL
MSB
HIGH IMPEDANCE
t_CYC
...
t_WH
t_FI
...
t_CS
t_RI
LSB
t_LAG
Output Timing
CS
SCK
SO
SI ^ADDR
t_V
MSB
...
t_HO
...
t_DIS
LSB
Submit Document Feedback ₁₅
FN8166.6
December 3, 2014