ISL6551_15 Datasheet, PDF (8/27 Pages) Intersil Corporation – ZVS Full Bridge PWM Controller

ISL6551
Electrical Specifications These specifications apply for V_DD = VDDP = 12V and T_A = 0°C to +85°C (ISL6551IB) or -40°C to +105°C
(ISL6551AB), Unless Otherwise Stated. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Leading Edge Blanking Adjust Range
(Figure 11)
50
300
ns
Leading Edge Blanking
t_LEB
R_LEB = 20k
R_LEB = 140k
64
ns
302
ns
R_LEB = 12V
0
ns
LATCHING SHUTDOWN (LATSD)
Fault Threshold
VIN
3
V
Fault_NOT Threshold
VINN
1.9
V
Time to Set latch (Note 5)
TSET
415
ns
ON/OFF (ON/OFF)
Turn-off Threshold
OFF
0.8
V
Turn-on Threshold
ON
2
V
CURRENT SHARE (SHARE, CS_COMP) (Note 5)
Voltage Offset Between Error Amp
Voltage of Master and Slave
Vcs_offset SHARE = 30k
30
mV
Maximum Source Current To External Ics_source SHARE = 30k
Reference
190
µA
Maximum Correctable Deviation In
Reference Voltage Between Master
and Slave
SHARE = 30K, Rsource = 1k,
OUTPUT REFERENCE = 1 to 5V,
(See Figure 13)
190
mV
Share/Adjust Loop Bandwidth
CS BW CS_COMP = 0.1µF
500
Hz
DCOK (DCOK)
Sink Current
Saturation Voltage
Input Reference
I_DCOK
V_SATDCOK
Vref_in
I_DCOK = 5mA
5
mA
0.4
V
1
5
V
Threshold (relative to Vref_in)
OV
(Figure 14)
5
%
Recovery (relative to Vref_in)
OV
(Figure 14)
3
%
Threshold (relative to Vref_in)
UV
(Figure 14)
-5
%
Recovery (relative to Vref_in)
UV
(Figure 14)
-3
%
Transient Rejection (Note 5)
TRej 100mV transient on Vout (system implicit rejection
250
µs
and feedback network dependence (Figure 15)
NOTE:
5. Established by design. Not 100% tested in production.
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8
FN9066.6
April 30, 2015