ISL6551_15 Datasheet, PDF (10/27 Pages) Intersil Corporation – ZVS Full Bridge PWM Controller

Shutdown Timing Diagrams
LATSD
ISL6551
C
LATCH CANNOT BE RESET BY ON/OFF
ON/OFF
VDD
ILIM_OUT
A
PKILIM > BGREF
B
PKILIM < BGREF
D
E
VDD_ON
LATCH RESET BY
REMOVING VDD
F
VDD_OFF
SOFT
START
DRIVER
ENABLE
SOFT-START
SHUTDOWN
FAULT
FAULT
OFF
OVER
CURRENT
LATCHED
OFF/ON
LATCH
RESET
UNDER VOLTAGE
LOCKOUT
FIGURE 3. SHUTDOWN TIMING DIAGRAMS
Shutdown Timing Descriptions
A (ON/OFF) - When the ON/OFF is pulled low, the soft-start
capacitor is discharged and all the drivers are disabled. When the
ON/OFF is released without a fault condition, a soft-start is
initiated.
B (OVERCURRENT) - If the output of the converter is over loaded,
i.e., the PKILIM is above the bandgap reference voltage (BGREF),
the soft-start capacitor is discharged very quickly and all the
drivers are turned off. Thereafter, the soft-start capacitor is
charged slowly and discharged quickly if the output is overloaded
again. The soft-start will remain in hiccup mode as long as the
overload conditions persist. Once the overload is removed, the
soft-start capacitor is charged up and the converter is then back
to normal operation.
C (LATCHING SHUTDOWN) - The IC is latched off completely as the
LATSD pin is pulled high and the soft-start capacitor is reset.
D (ON/OFF) - The latch cannot be reset by the ON/OFF.
E (LATCH RESET) - The latch is reset by removing the VDD. The
soft-start capacitor starts to be charged after VDD increases
above the turn-on threshold VDD_ON.
F (VDD UVLO) - The IC is turned off when the VDD is below the
turn-off threshold VDD_OFF. Hysteresis VDD_HYS is incorporated in
the undervoltage lockout (UVLO) circuit.
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FN9066.6
April 30, 2015