ISL6551_15 Datasheet, PDF (7/27 Pages) Intersil Corporation – ZVS Full Bridge PWM Controller

ISL6551
Electrical Specifications These specifications apply for V_DD = VDDP = 12V and T_A = 0°C to +85°C (ISL6551IB) or -40°C to +105°C
(ISL6551AB), Unless Otherwise Stated. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ERROR AMPLIFIER (EANI, EAI, EAO) (Note 5)
Unity Gain Bandwidth
UGBW
10
MHz
DC Gain
DCG
79
dB
Maximum Offset Error Voltage
Vos
3.1
mV
Input Common Mode Range
Common Mode Rejection Ratio
Vcm
CMMR
V_DD = 12V
0.4
9
V
82
dB
Power Supply Rejection Ratio
PSSR 1mA load
95
dB
Maximum Output Source Current
ISRC
2
mA
Maximum Lower Saturation Voltage
Vsatlow Sinking 0.27mA
125
mV
RAMP ADJUST (R_RA) (Note 5)
Ramp Frequency
F
100
1000
kHz
Linear Voltage Ramp, Minimum
LVR
50
mV
Linear Voltage Ramp, Maximum
250
mV
Overall Variation
25
%
PEAK CURRENT LIMIT (PKILIM)
Peak Current Shutdown Threshold
IpkThr BGREF = 0.1µF, 399kΩ pull-up
1.25 1.263 1.31
V
Peak Current Shutdown Delay (Note 5) IpkDel
75
ns
SOFT-START (CSS)
Charge Current
Iss
Vcss = 0.6V
8
12
µA
Discharge Current
Idis
1.6
5.2
mA
Cycle-by-cycle Current Limit
(ISL6551IB)
Vclamp
2
8
V
Cycle-by-cycle Current Limit
(ISL6551AB)
Vclamp
1.9
8.1
V
DRIVERS (UPPER1, UPPER2, LOWER1, LOWER2)
Maximum Capacitive Load (each)
CL
VDD = VDDP = 12V, F = 1MHz,
1600
pF
Thermal Dependence
Turn-on Rise Time (ISL6551IB)
tr
1.0nF Capacitive load
8.9
16
ns
Turn-on Rise Time (ISL6551AB)
tr
1.0nF Capacitive load
9.2
17
ns
Turn-off Fall Time (ISL6551IB)
tf
1.0nF Capacitive load
6.4
10
ns
Turn-off Fall Time (ISL6551AB)
Shutdown Delay (Note 5)
Rising Edge Delay (Note 5)
Falling Edge Delay (Note 5)
Vsat_sourcing
tf
t_SD
t_RD
t_FD
Vsat_high
1.0nF Capacitive load
1.0nF Capacitive load
1.0nF Capacitive load
1.0nF Capacitive load
Sourcing 20mA
12
ns
14.5
ns
16.4
ns
13.7
ns
1.00
V
Sourcing 200mA
1.35
V
Vsat_sinking (ISL6551IB)
Vsat_low Sinking 20mA
0.035
V
Sinking 200mA
0.31
V
Vsat_sinking (ISL6551AB)
Vsat_low Sinking 20mA
0.04
V
Sinking 200mA
0.5
V
SYNCHRONOUS SIGNALS (SYNC1, SYNC2)
Maximum capacitive load (each)
PROGRAMMABLE DELAYS (RESDLY, LEB) (Note 5)
V_DD = 12, F = 1MHz
20
pF
Resonant Delay Adjust Range
(Figure 10)
50
500
ns
Resonant Delay
t_RESDLY
R_RESDLY = 10k
R_RESDLY = 120k
55
ns
488
ns
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7
FN9066.6
April 30, 2015