ISL6551_15 Datasheet, PDF (16/27 Pages) Intersil Corporation – ZVS Full Bridge PWM Controller

ISL6551
• Power-good (DCOK)
- DCOK pin is an open-drain output capable of sinking 5mA.
It is low when the output voltage is within the UVOV
window. The static regulation limit is ±3%, while the ±5%
is the dynamic regulation limit. It indicates power-good
when the EAI is within -3% to +5% on the rising edge and
within +3% to -5%on the falling edge, as shown in
Figure 14.
EAI
+5%
+3%
EANI
-3%
-5%
DCOK
FAULT
FIGURE 14. UNDERVOLTAGE-OVERVOLTAGE WINDOW
- The DCOK comparator might not be triggered even though
the output voltage exceeds ±5% limits at load transients.
This is because the feedback network of the error amplifier
filters out part of the transients and the EAI only sees the
remaining portion that is still within the limits, as illustrated
in Figure 15. The lower the “zero (1/RC)” of the error
amplifier, the larger the portion of the transient is filtered
out.
18K
15N
EAI R
C
VOUT
1K _EANI
-
+
EAO
1.10V
1.00V
VOUT
0.90V
1.05V
1.00V
0.95V
EAI
FIGURE 15. OUTPUT TRANSIENT REJECTION
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FN9066.6
April 30, 2015