ISL6551_15 Datasheet, PDF (13/27 Pages) Intersil Corporation – ZVS Full Bridge PWM Controller

ISL6551
- Per Equation 3, the clamping voltage is a function of the
charge current Iss. For a more predictable clamping
voltage, the CSS pin can be connected to a reference-
based clamp circuit as shown in Figure 8. To make the
Vclamp less dependent on the soft-start current (Iss), the
currents flowing through R₁ and R₂ should be scaled
much greater than Iss. The relationship of this circuit can
be found in Equation 4.
V_REF
R₁
CSS
R₂
FIGURE 8. REFERENCE-BASED CLAMP CIRCUIT
Vclamp  Iss  _R-R----11----+-^----RR-----²²- + Vref  -R----₁---R--+--²---R----₂-
(EQ. 4)
- The soft-start rise time (T_ss) can be calculated with
Equation 5. The rise time (T_rise) of the output voltage is
approximated with Equation 6.
tss = ^{V-----c---l--a----m--I--s--p--s--}-----C-----s---s--
(s)
(EQ. 5)
t_rise = -E----A----N----I-I-s--^-s----C-----s---s--
(s)
(EQ. 6)
• Drivers (Upper1, Upper2, Lower1, Lower2)
- The two upper drivers are driven at a fixed 50% duty cycle
and the two lower drivers are PWM controlled on the
trailing edge while the leading edge employs resonant delay.
They are biased by VDDP1 and VDDP2, respectively.
- Each driver is capable of driving capacitive loads up to CL at
1MHz clock frequency and higher loads at lower frequencies
on a layout with high effective thermal conductivity.
- The UVLO holds all the drivers low until the VDD has reached
the turn-on threshold VDD_ON.
- The upper drivers require assistance of external level-shifting
circuits such as Intersil’s HIP2100 or pulse transformers to
drive the upper power switches of a bridge converter.
• Peak Current Limit (PKILIM)
- When the voltage at PKILIM exceeds the BGREF voltage, the
gate pulses are terminated and held low until the next clock
cycle. The peak current limit circuit has a high-speed loop
with propagation delay IpkDel. Peak current shutdown
initiates a soft-start sequence.
- The peak current shutdown threshold is usually set slightly
higher than the normal cycle-by-cycle PWM peak current
limit (Vclamp) and therefore will normally only be activated
in a short-circuit condition. The limit can be set with a resistor
divider from the ISENSE pin. The resistor divider relationship
is defined in Equation 7.
- In general, the trip point is a little smaller than the BGREF
due to the noise and/or ripple at the BGREF.
R_UP
R_DOWN
ISENSE
PKILIM
FIGURE 9. PEAK CURRENT LIMIT SET CIRCUIT
-R----_D----_O-R----_WD-----^ON----^W-+-----^N_R-----U----_P-- = _{I---S----E---B--N---G-S----R-E----E}---m-F----a----x---_-
(EQ. 7)
• Latching Shutdown (LATSD)
- A high TTL level on LATSD latches the IC off. The IC goes into
a low power mode and is reset only after the power at the
VDD pin is removed completely. The ON/OFF cannot reset
the latch.
- This pin can be used to latch the power supply off on output
overvoltage or other undesired conditions.
• ON/OFF (ON/OFF)
- A high standard TTL input (safe also for VDD level) signals the
controller to turn on. A low TTL input turns off the controller
and terminates all drive signals including the SYNC outputs.
The soft-start is reset.
- This pin is a non-latching input and can accept an enable
command when monitoring the input voltage and the
thermal condition of a converter.
• Resonant Delay (R_RESDLY)
- A resistor tied between R_RESDLY and VSS determines the
delay that is required to turn on a lower FET after its
corresponding upper FET is turned off. This is the resonant
delay, which can be estimated with Equation 8.
t_RESDLY = 4.01 x R_RESDLY/k + 13 (ns)
(EQ. 8)
- Figure 10 illustrates the relationship of the value of the
resistor (R_RESDLY) and the resonant delay (t_RESDLY). The
percentages in the figure are the tolerances at the two end
points of the curve.
500
450
400
350
300
250
200
150
100 ^+37%
+4%
50
0
20
40
60
80
R_RESDLY (kΩ)
+18%
-24%
100
120
FIGURE 10. R_RESDLY vs RESDLY
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FN9066.6
April 30, 2015