ISL6551_15 Datasheet, PDF (15/27 Pages) Intersil Corporation – ZVS Full Bridge PWM Controller

ISL6551
• Ramp Adjust (R_RA, ISENSE)
- The ramp adjust block adds an offset component
(200mV) and a slope adjust component to the ISENSE
signal before processing it at the PWM Logic block, as
shown in Figure 12. This ensures that the ramp voltage is
always higher than the OAGS (ground sensing opamp)
minimum voltage to achieve a “zero” state.
- It is critical that the input signal to ISENSE decays to zero
prior to or during the clock dead time. The level-shifting
and capacitive summing circuits in the RAMP ADJUST
block are reset during the dead time. Any input signal
transitions that occur after the rising edge of CLK and
prior to the rising edge of RESDLY can cause severe errors
in the signal reaching the PWM comparator.
- Typical ramp values are hundreds of mV over the period
on a 3V full scale current. Too much ramp makes the
controller look like a voltage mode PWM and too little
ramp leads to noise issues (jitter). The amount of ramp
(V_ramp), as shown in Figure 12, is programmed with the
R_RA resistor and can be calculated with Equation 10.
V_ramp = BGREF x dt /(R_RA x 500E-12) (V)
(EQ. 10)
Where dt = Duty Cycle / f_SW - t_LEB (s). Duty cycle is
discussed in detail in application note AN1002.
- The voltage representation of the current flowing
through the power train at ISENSE pin is normally scaled
such that the desired peak current is less than or equal
to Vclamp-200mV-V_ramp, where the clamping voltage is
set at the CSS pin.
• SYNC Outputs (SYNC1, SYNC2)
- SYNC1 and SYNC2 are the gate control signals for the
output synchronous rectifiers. They are biased by V_DD and
are capable of driving capacitive loads up to 20pF at
1MHz clock frequency (500kHz switching frequency).
These outputs are turned off sooner than the turn-off at
UPPER1 and UPPER2 by the clock dead time, DT.
- Inverting both SYNC signals or both LOWER signals is
another possible way to control the drivers of the
synchronous rectifiers. When using these drive schemes,
the user should understand the issues that might occur in
his/her applications, especially the impacts on current
share operation and light load operation. Refer to
application note AN1002 for more details.
- External high current drivers controlled by the
synchronous signals are required to drive the synchronous
rectifiers. A pulse transformer is required to pass the drive
signals to the secondary side if the IC is used in a primary
control system.
• Share Support (SHARE, CS_COMP)
- The unit with the highest reference is the master. Other
units, as slaves, adjust their references via a source
resistor to match the master reference sharing the load
current. The source resistor is typically 1kΩ connecting
the EANI pin and the OUTPUT REFERENCE (external
reference or BGREF), as shown in Figure 13. The share
bus represents a 30kΩ resistive load per unit, up to 10
units.
- The output (ADJ) of “Operational Transconductance
Amplifier (OTA)” can only pull high and it is floating while
in master mode. This ensures that no current is sourced to
the OUTPUT REFERENCE when the IC is working by itself.
- The slave units attempt to drive their error amplifier
voltage to be within a predetermined offset (30mV
typical) of the master error voltage (the share bus). The
current-share error is nominally (30mV/EAO)*100%
assuming no other source of error. With a 2.5V full load
error amp voltage, the current-share error at full load
would be -1.2% (slaves relative to master).
- The bandwidth of the current sharing loop should be
much lower than that of the voltage loop to eliminate
noise pickup and interactions between the voltage
regulation loop and the current loop. A 0.1µF capacitor is
recommended between CS_COMP and VSS pins to
achieve a low current sharing loop bandwidth (100Hz to
500Hz).
EAO
+
-
30mV
- ADJ
+
OTA
CS_COMP
0.1µF
1k
EANI
(+)
SHARE
OUTPUT
REFERENCE
30k
FIGURE 13. SIMPLIFIED CURRENT SHARE CIRCUIT
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FN9066.6
April 30, 2015