ISL6551_15 Datasheet, PDF (19/27 Pages) Intersil Corporation – ZVS Full Bridge PWM Controller

Current Sense
Q3_S
T_CURRENT
Q4_S
ISL6551
I_SENSE
V_INF
CURRENT_SEN_P
I_SENSE
FIGURE 18A. TWO-LEG SENSE
Q3_S and Q4_S
R_SENSE
FIGURE 18B. TOP SENSE
I_SENSE
FIGURE 18C. RESISTOR SENSE (PRIMARY CONTROL)
FIGURE 18. CURRENT SENSE
Primary FETs
V_INF
or CURRENT_SEN_P
Q1_G
P–
Q1
Q2_G
Q2
P+
P1–
P2–
Q3_G
Q3
Q4_G
Q4
Q3_G
Q3
Q4_G
Q4
Q3_S
FIGURE 19A. FULL BRIDGE
Q4_S
FIGURE 19. PRIMARY FETs
Q3_S
Q4_S
FIGURE 19B. PUSH-PULL
Two-leg Sense- Senses the current that flows through both lower
primary FETs. Operates at the switching frequency.
Top Sense- Senses the sum of the current that flows through both
upper primary FETs. Operates at the clock frequency.
Resistor Sense- This simple scheme is used in a primary side
control system. The sum of the current that flows through both
lower primary FETs is sensed with a low impedance power
resistor. The sources of Q3 and Q4 and ISENSE should be tied at
the same point as close as possible.
BIASES
Linear Regulator- In a primary side control system, a linear
regulator derived from the input line can be used for the
start-up purpose and an extra winding coupled with the main
transformer can provide the controller power after the start
up.
DCM Flyback- Use a PWM controller to develop both primary
and secondary biases with discontinuous current mode
flyback topology
Full Bridge- Four MOSFETs are required for full bridge
converters. The drain-to-source voltage rating of the MOSFETs
is V_IN.
Push-pull- Only the two lower MOSFETs are required for
push-pull converters. The two upper drivers are not used. The
V_DS of the MOSFETs is 2xV_IN.
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FN9066.6
April 30, 2015