ISL6323 Datasheet, PDF (8/34 Pages) Intersil Corporation – Hybrid SVI/PVI

ISL6323
Electrical Specifications Recommended Operating Conditions (0°C to +70°C), Unless Otherwise Specified. (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
LGATE Rise Time
t_RLGATE; V_PVCC = 12V, 3nF Load, 10% to 90%
18
UGATE Fall Time
t_FUGATE; V_PVCC = 12V, 3nF Load, 90% to 10%
18
LGATE Fall Time
t_FLGATE; V_PVCC = 12V, 3nF Load, 90% to 10%
12
UGATE Turn-On Non-overlap
t_PDHUGATE; V_PVCC = 12V, 3nF Load, Adaptive
10
LGATE Turn-On Non-overlap
t_PDHLGATE; V_PVCC = 12V, 3nF Load, Adaptive
10
GATE DRIVE RESISTANCE (Note 3)
Upper Drive Source Resistance
Upper Drive Sink Resistance
Lower Drive Source Resistance
Lower Drive Sink Resistance
MODE SELECTION
V_PVCC = 12V, 15mA Source Current
V_PVCC = 12V, 15mA Sink Current
V_PVCC = 12V, 15mA Source Current
V_PVCC = 12V, 15mA Sink Current
2.0
1.65
1.25
0.80
VID1/SEL Input Low
EN taken from HI to LO, VDDIO = 1.5V
0.45
VID1/SEL Input High
EN taken from LO to HI, VDDIO = 1.5V
1.00
PVI INTERFACE
VIDx Pull-down
VDDIO = 1.5V
30
45
VIDx Input Low
VDDIO = 1.5V
0.45
VIDx Input High
VDDIO = 1.5V
1.00
SVI INTERFACE
SVC, SVD Input LOW (VIL)
0.4
SVC, SVD Input HIGH (VIH)
1.10
Schmitt Trigger Input Hysteresis
0.14
0.35
0.55
SVD Low Level Output Voltage
3mA Sink Current
0.285
Maximum SVC, SVD Leakage (Note 3)
±5
UNITS
ns
ns
ns
ns
ns
Ω
Ω
Ω
Ω
V
V
µA
V
V
V
V
V
V
µA
Timing Diagram
UGATE
LGATE
t_PDHUGATE
t_FLGATE
t_RUGATE
t_FUGATE
t_PDHLGATE
t_RLGATE
8
FN9278.2
April 7, 2008