ISL6323 Datasheet, PDF (18/34 Pages) Intersil Corporation – Hybrid SVI/PVI

ISL6323
Voltage Regulation
The integrating compensation network shown in Figure 8
insures that the steady-state error in the output voltage is
limited only to the error in the reference voltage and offset
errors in the OFS current source, remote-sense and error
amplifiers. Intersil specifies the guaranteed tolerance of the
ISL6323 to include the combined tolerances of each of these
elements.
The output of the error amplifier, V_COMP, is used by the
modulator to generate the PWM signals. The PWM signals
control the timing of the Internal MOSFET drivers and
regulate the converter output so that the voltage at FB is equal
to the voltage at REF. This will regulate the output voltage to
be equal to Equation 11. The internal and external circuitry
that controls voltage regulation is illustrated in Figure 8.
V_OUT = V_REF – V_OFS – V_DROOP
(EQ. 11)
The ISL6323 incorporates differential remote-sense
amplification in the feedback path. The differential sensing
removes the voltage error encountered when measuring the
output voltage relative to the controller ground reference point
resulting in a more accurate means of sensing output voltage.
EXTERNAL CIRCUIT
FS
R_FS
COMP
ISL6323 INTERNAL CIRCUIT
DROOP
CONTROL
TO
OSCILLATOR
C_C
R_C
FB
R_FB
+
(V_DROOP + V_OFS)
-
+
V_OUT
-
VSEN
RGND
I_AVG
I_OFS
-
V_COMP
+ _ERROR
AMPLIFIER
∑⁺
+
VID
DAC
FIGURE 8. OUTPUT VOLTAGE AND LOAD-LINE
REGULATION WITH OFFSET ADJUSTMENT
Load-Line (Droop) Regulation
By adding a well controlled output impedance, the output
voltage can effectively be level shifted in a direction which
works to achieve a cost-effective solution can help to reduce
the output-voltage spike that results from fast load-current
demand changes.
The magnitude of the spike is dictated by the ESR and ESL
of the output capacitors selected. By positioning the no-load
voltage level near the upper specification limit, a larger
negative spike can be sustained without crossing the lower
limit. By adding a well controlled output impedance, the
output voltage under load can effectively be level shifted
down so that a larger positive spike can be sustained without
crossing the upper specification limit.
As shown in Figure 8, with the FS resistor tied to ground, the
average current of all active channels, I_AVG, flows from FB
through a load-line regulation resistor R_FB. The resulting
voltage drop across R_FB is proportional to the output current,
effectively creating an output voltage droop with a steady-
state value defined as in Equation 12:
V_DROOP = I_AVG ⋅ R_FB
(EQ. 12)
The regulated output voltage is reduced by the droop voltage
V_DROOP. The output voltage as a function of load current is
shown in Equation 13.
V_OUT
=
V_REF
–
V_O
F
S
–
⎛
⎜
⎝
-^I-^O-----^U----^T--
N
⋅
D
CR
⋅
⎛
⎝
4_----0_---0_--
3
⋅
-_R----_S--¹--_E----_T- _⎠⎞
⋅K⋅
⎞
R_{F B⎠⎟}
(EQ. 13)
In Equation 13, V_REF is the reference voltage, V_OFS is the
programmed offset voltage, I_OUT is the total output current
of the converter, K is the DC gain of the RC filter across the
inductor (K is defined in Equation 7), N is the number of
active channels, and DCR is the Inductor DCR value.
Output-Voltage Offset Programming
The ISL6323 allows the designer to accurately adjust the
offset voltage by connecting a resistor, R_OFS, from the OFS
pin to VCC or GND. When R_OFS is connected between OFS
and VCC, the voltage across it is regulated to 1.6V. This
causes a proportional current (I_OFS) to flow into the FB pin
and out of the OFS pin. If R_OFS is connected to ground, the
voltage across it is regulated to 0.3V, and I_OFS flows into the
OFS pin and out of the FB pin. The offset current flowing
through the resistor between VDIFF and FB will generate the
desired offset voltage which is equal to the product
(I_OFS x R_FB). These functions are shown in Figures 9 and
10.
Once the desired output offset voltage has been determined,
use Equations 14 and 15 to set R_OFS:
For Positive Offset (connect R_OFS to GND):
R_OFS
=
-⁰---^.--³-----^×----^R-----^F----^B--
V_OFFSET
(EQ. 14)
For Negative Offset (connect R_OFS to VCC):
R_OFS
=
-¹---^.--⁶-----^×----^R-----^F----^B--
V_OFFSET
(EQ. 15)
18
FN9278.2
April 7, 2008