ISL6323 Datasheet, PDF (28/34 Pages) Intersil Corporation – Hybrid SVI/PVI

ISL6323
resistors based on the original values, R_1(OLD) and
R_2(OLD) using Equations 47 and 48.
R_1(NEW)
=
R_1(OLD)
⋅
Δ_----V_----1-
ΔV₂
(EQ. 47)
R_2(1)(NEW)
=
R_2(OLD)
⋅
Δ_----V_----1-
ΔV₂
(EQ. 48)
4. Replace R₁ and R₂ with the new values and check to see
that the error is corrected. Repeat the procedure if
necessary.
C₂ (OPTIONAL)
R_C ^CC
COMP
R_FB
FB
ISL6323
VSEN
ΔV₂
ΔV₁
V_OUT
I_TRAN
ΔI
FIGURE 21. TIME CONSTANT MISMATCH BEHAVIOR
Loadline Regulation Resistor
The loadline regulation resistor, labeled R_FB in Figure 8,
sets the desired loadline required for the application.
Equation 49 can be used to calculate R_FB.
R_FB
=
-----------------^V----^D----^R----^O-----^O----^P----^M-----^A----^X------------------
4_----0_---0_--
3
⋅
I_{--O-----U----T----M----A----X--}
N
⋅
-^D-----^C-----^R---
R_SET
⋅
K
(EQ. 49)
Where K is defined in Equation 7.
If no loadline regulation is required, FS resistor should be
tied between the FS pin and VCC. To choose the value for
R_FB in this situation, please refer to “Compensation Without
Loadline Regulation” on page 29.
Compensation With Loadline Regulation
The load-line regulated converter behaves in a similar
manner to a peak current mode controller because the two
poles at the output filter LC resonant frequency split with the
introduction of current information into the control loop. The
final location of these poles is determined by the system
function, the gain of the current signal, and the value of the
compensation components, R_C and C_C.
FIGURE 22. COMPENSATION CONFIGURATION FOR
LOAD-LINE REGULATED ISL6323 CIRCUIT
Since the system poles and zero are affected by the values
of the components that are meant to compensate them, the
solution to the system equation becomes fairly complicated.
Fortunately, there is a simple approximation that comes very
close to an optimal solution. Treating the system as though it
were a voltage-mode regulator, by compensating the LC
poles and the ESR zero of the voltage mode approximation,
yields a solution that is always stable with very close to ideal
transient performance.
Select a target bandwidth for the compensated system, f₀.
The target bandwidth must be large enough to assure
adequate transient performance, but smaller than 1/3 of the
per-channel switching frequency. The values of the
compensation components depend on the relationships of f₀
to the LC pole frequency and the ESR zero frequency. For
each of the following three, there is a separate set of
equations for the compensation components.
In Equation 50, L is the per-channel filter inductance divided
by the number of active channels; C is the sum total of all
output capacitors; ESR is the equivalent series resistance of
the bulk output filter capacitance; and V_P-P is the peak-to-
peak sawtooth signal amplitude as described in the
“Electrical Specifications” table on page 6.
Once selected, the compensation values in Equation 50
assure a stable converter with reasonable transient
performance. In most cases, transient performance can be
improved by making adjustments to R_C. Slowly increase the
value of R_C while observing the transient performance on an
oscilloscope until no further improvement is noted. Normally,
C_C will not need adjustment. Keep the value of C_C from
Equation 50 unless some performance issue is noted.
The optional capacitor C₂, is sometimes needed to bypass
noise away from the PWM comparator (see Figure 22). Keep
a position available for C₂, and be prepared to install a high
frequency capacitor of between 22pF and 150pF in case any
leading edge jitter problem is noted.
28
FN9278.2
April 7, 2008