ISL6323 Datasheet, PDF (20/34 Pages) Intersil Corporation – Hybrid SVI/PVI

ISL6323
K1
=
----^V----^I--^N-----
V_{P – P}
A
=
-----^K-----¹------
K1 – 1
R_RCOMP = A × R_C
(EQ. 16)
(EQ. 17)
C_RCOMP
=
C_-----C--
A
(EQ. 18)
Advanced Adaptive Zero Shoot-Through Deadtime
Control (Patent Pending)
The integrated drivers incorporate a unique adaptive deadtime
control technique to minimize deadtime, resulting in high
efficiency from the reduced freewheeling time of the lower
MOSFET body-diode conduction, and to prevent the upper and
lower MOSFETs from conducting simultaneously. This is
accomplished by ensuring either rising gate turns on its
MOSFET with minimum and sufficient delay after the other has
turned off.
During turn-off of the lower MOSFET, the PHASE voltage is
monitored until it reaches a -0.3V/+0.8V (forward/reverse
inductor current). At this time the UGATE is released to rise. An
auto-zero comparator is used to correct the r_DS(ON) drop in the
phase voltage preventing false detection of the -0.3V phase
level during r_DS(ON) conduction period. In the case of zero
current, the UGATE is released after 35ns delay of the LGATE
dropping below 0.5V. When LGATE first begins to transition
low, this quick transition can disturb the PHASE node and
cause a false trip, so there is 20ns of blanking time once
LGATE falls until PHASE is monitored.
Once the PHASE is high, the advanced adaptive
shoot-through circuitry monitors the PHASE and UGATE
voltages during a PWM falling edge and the subsequent
UGATE turn-off. If either the UGATE falls to less than 1.75V
above the PHASE or the PHASE falls to less than +0.8V, the
LGATE is released to turn-on.
Initialization
Prior to initialization, proper conditions must exist on the EN,
VCC, PVCC1_2, PVCC_NB, ISEN3-, and ISEN4- pins. When
the conditions are met, the controller begins soft-start. Once
the output voltage is within the proper window of operation,
the controller asserts VDDPWRGD.
Power-On Reset
The ISL6323 requires VCC, PVCC1_2, and PVCC_NB
inputs to exceed their rising POR thresholds before the
ISL6323 has sufficient bias to guarantee proper operation.
The bias voltage applied to VCC must reach the internal
power-on reset (POR) rising threshold. Once this threshold
is reached, the ISL6323 has enough bias to begin checking
the driver POR inputs, EN, and channel detect portions of
the initialization cycle. Hysteresis between the rising and
falling thresholds assure the ISL6323 will not advertently
turn off unless the bias voltage drops substantially (see
“Electrical Specifications” on page 6).
20
ISL6323 INTERNAL CIRCUIT
EXTERNAL CIRCUIT
VCC
PVCC1_2
POR
CIRCUIT
PVCC_NB
+12V
ENABLE
COMPARATOR
+
-
10.7kΩ
EN
1.00kΩ
V_{EN_THR}
SOFT-START
AND
FAULT LOGIC
CHANNEL
DETECT
ISEN3-
ISEN4-
FIGURE 12. POWER SEQUENCING USING THRESHOLD-
SENSITIVE ENABLE (EN) FUNCTION
The bias voltage applied to the PVCC1_2 and PVCC_NB
pins power the internal MOSFET drivers of each output
channel. In order for the ISL6323 to begin operation, both
PVCC inputs must exceed their POR rising threshold to
guarantee proper operation of the internal drivers.
Hysteresis between the rising and falling thresholds assure
that once enabled, the ISL6323 will not inadvertently turn off
unless the PVCC bias voltage drops substantially (see
“Electrical Specifications” on page 6). Depending on the
number of active CORE channels determined by the Phase
Detect block, the external driver POR checking is supported
by the Enable Comparator.
Enable Comparator
The ISL6323 features a dual function enable input (EN) for
enabling the controller and power sequencing between the
controller and external drivers or another voltage rail. The
enable comparator holds the ISL6323 in shutdown until the
voltage at EN rises above 0.86V. The enable comparator has
about 110mV of hysteresis to prevent bounce. It is important
that the driver ICs reach their rising POR level before the
ISL6323 becomes enabled. The schematic in Figure 12
demonstrates sequencing the ISL6323 with the ISL66xx
family of Intersil MOSFET drivers, which require 12V bias.
When selecting the value of the resistor divider the driver
maximum rising POR threshold should be used for
calculating the proper resistor values. This will prevent
improper sequencing events from creating false trips during
soft-start.
If the controller is configured for 2-phase CORE operation,
then the resistor divider can be used for sequencing the
FN9278.2
April 7, 2008