ISL6323 Datasheet, PDF (19/34 Pages) Intersil Corporation – Hybrid SVI/PVI

ISL6323
VDIFF
-
V_OFS
+
R_FB
FB
I_OFS
VREF
+
E/A
-
+
-
VCC
R_OFS
OFS
ISL6323
-
-
+
1.6V
+
+
0.3V
-
GND
VCC
FIGURE 9. NEGATIVE OFFSET OUTPUT VOLTAGE
PROGRAMMING
V_OUT
+
V_OFS
-
R_FB
FB
I_OFS
VREF
+
E/A
-
+
-
R_OFS
OFS
ISL6323
GND
-
+
+
0.3V
-
-
1.6V
+
GND
VCC
FIGURE 10. POSITIVE OFFSET OUTPUT VOLTAGE
PROGRAMMING
Dynamic VID
The AMD processor does not step the output voltage
commands up or down to the target voltage, but instead
passes only the target voltage to the ISL6323 through either
the PVI or SVI interface. The ISL6323 manages the resulting
VID-on-the-Fly transition in a controlled manner, supervising
a safe output voltage transition without discontinuity or
disruption. The ISL6323 begins slewing the DAC at
3.25mV/µs until the DAC and target voltage are equal. Thus,
the total time required for a dynamic VID transition is
dependent only on the size of the DAC change.
To further improve dynamic VID performance, ISL6323 also
implements a proprietary DAC smoothing feature. The
external series RC components connected between DVC
and FB limit any stair-stepping of the output voltage during a
VID-on-the-Fly transition.
Compensating Dynamic VID Transitions
During a VID transition, the resulting change in voltage on
the FB pin and the COMP pin causes an AC current to flow
through the error amplifier compensation components from
the FB to the COMP pin. This current then flows through the
feedback resistor, R_FB, and can cause the output voltage to
overshoot or undershoot at the end of the VID transition. In
order to ensure the smooth transition of the output voltage
during a VID change, a VID-on-the-fly compensation
network is required. This network is composed of a resistor
and capacitor in series, R_DVC and C_DVC, between the DVC
and the FB pin.
VSEN
R_FB ^IDVC ^{= I}C
I_C
I_DVC
C_DVC
DVC
R_DVC
C_C
FB
R_C
COMP
2X
VDAC+RGND
-
+ _ERROR
AMPLIFIER
ISL6323 INTERNAL CIRCUIT
FIGURE 11. DYNAMIC VID COMPENSATION NETWORK
This VID-on-the-fly compensation network works by
sourcing AC current into the FB node to offset the effects of
the AC current flowing from the FB to the COMP pin during a
VID transition. To create this compensation current the
ISL6323 sets the voltage on the DVC pin to be 2x the voltage
on the REF pin. Since the error amplifier forces the voltage
on the FB pin and the REF pin to be equal, the resulting
voltage across the series RC between DVC and FB is equal
to the REF pin voltage. The RC compensation components,
R_DVC and C_DVC, can then be selected to create the desired
amount of compensation current.
The amount of compensation current required is dependant
on the modulator gain of the system, K1, and the error
amplifier RC components, R_C and C_C, that are in series
between the FB and COMP pins. Use Equations 16, 17 and
18 to calculate the RC component values, R_DVC and C_DVC,
for the VID-on-the-fly compensation network. For these
equations: V_IN is the input voltage for the power train; V_P-P
is the oscillator ramp amplitude (1.5V); and R_C and C_C are
the error amplifier RC components between the FB and
COMP pins.
19
FN9278.2
April 7, 2008