X98021 Datasheet, PDF (7/29 Pages) Intersil Corporation – 210MHz Triple Video Digitizer with Digital PLL

X98021
HSYNC_IN
Analog
Video In
DATACLK
The HSYNC edge (programmable leading or trailing) that the DPLL is locked to.
The sampling phase setting determines its relative position to the rest of the AFE’s output signals
t_{HSYNCin-to-HSout} = 7.5ns + (PHASE/64 +10.5)*t_PIXEL
P₀
P₁
P₂
P₃
P₄
P₅
P₆
P₇
P₈
P₉
P₁₀
P₁₁
P₁₂
R_P/G_P/B_P[7:0]
R_S/G_S/B_S[7:0]
HS_OUT
Programmable
Width and Polarity
FIGURE 5. 48 BIT OUTPUT MODE
D₀
D₂
D₁
D₃
HSYNC_IN
Analog
Video In
DATACLK
R_P/G_P/B_P[7:0]
R_S/G_S/B_S[7:0]
HS_OUT
The HSYNC edge (programmable leading or trailing) that the DPLL is locked to.
The sampling phase setting determines its relative position to the rest of the AFE’s output signals
t_{HSYNCin-to-HSout} = 7.5ns + (PHASE/64 +8.5)*t_PIXEL
P₀
P₁
P₂
P₃
P₄
P₅
P₆
P₇
P₈
P₉
P₁₀
P₁₁
Programmable
Width and Polarity
FIGURE 6. 48 BIT OUTPUT MODE, INTERLEAVED TIMING
D₀
D₂
D₁
7
FN8219.0
June 2, 2005