X98021 Datasheet, PDF (24/29 Pages) Intersil Corporation – 210MHz Triple Video Digitizer with Digital PLL

X98021
HSYNC_IN
(to A and B)
DPLL Lock Edge
Analog Video In
(to A and B)
P_N-3 P_N-2 P_N-1 P_N P₀ P₁ P₂ P₃ P₄ P₅ P₆ P₇ P₈ P₉ P₁₀ P₁₁ P₁₂
PIXELCLK (A)
(Internal)
DATACLK (A)
DATA_PRI (A)
DATA_SEC (A)
HS_OUT (A)
PIXELCLK (B)
(Internal)
DATACLK (B)
D_N-3
D₀
D_N-1
D₂
CLKINV_IN (A) = GND_D
½ PIXELCLK = ¼ DATACLK Delay
DATA_PRI (B)
D_N-2
D₁
DATA_SEC (B)
D_N
D₃
HS_OUT (B)
CLKINV_IN (B) = GND_D
FIGURE 10. ALTERNATE PIXEL SAMPLING (48 BIT MODE)
._{Initialization}
The X98021 initializes with default register settings for an
AC-coupled, RGB input on the VGA1 channel, with a 24 bit
output.
The following registers should be written to fully enable the
chip:
• Register 0x1C should be set to 0x49 to improve DPLL
performance in video modes
• Register 0x23 should be set to 0x78 to enable the DC
Restore function
Reset
The X98021 has a Power-On Reset (POR) function that
resets the chip to its default state when power is initially
applied, including resetting all the registers to their default
settings as described in the Register Listing. The external
RESET pin duplicates the reset function of the POR without
having to cycle the power supplies. The RESET pin does not
need to be used in normal operation and can be tied high.
Rare CSYNC Considerations
Intersil has discovered one anomaly in its sync separator
function. If the CSYNC signal shown in Figure 11 is present
on the HSYNC input, and the sync source is set to CSYNC
on HSYNC, HS_OUT may sporadically lock to the wrong edge
of HSYNC_IN. This will cause the HS_OUT to have the wrong
position relative to pixel 0, resulting in the image shifting left
or right by the width of the HSYNC_IN signal for about 1
second before it corrects itself.
This only happens with the exact waveshape shown in
Figure 11. If the polarity of the sync signal is inverted from
that shown in Figure 11, the problem will not occur. If there
are any serrations during the VSYNC period, the problem
will not occur. The problem also will not occur if the sync
signal is on the SOG input.
This is a rarely used composite sync format; in most
applications it will never be encountered. However if this
CSYNC waveform must be supported, there is a simple
applications solution using an XOR gate.
24
FN8219.0
June 2, 2005