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X98021 Datasheet, PDF (23/29 Pages) Intersil Corporation – 210MHz Triple Video Digitizer with Digital PLL
X98021
HSYNCIN
(to A and B)
DPLL Lock Edge
Analog Video In
(to A and B)
PN-3 PN-2 PN-1 PN P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12
DATACLK (A)
DATA (A)
DN-3
DN-1
D0
D2
HSOUT (A)
DATACLK (B)
CLKINVIN (A) = GNDD
½ DATACLK Delay
DATA (B)
DN-2
DN
D1 D3
HSOUT (B)
CLKINVIN (B) = VD
FIGURE 9. ALTERNATE PIXEL SAMPLING (24 BIT MODE)
Crystal Oscillator
An external 23MHz to 27MHz crystal supplies the low-jitter
reference clock to the DPLL. The absolute frequency of this
crystal within this range is unimportant, as is the crystal’s
temperature coefficient, allowing use of less expensive,
lower-grade crystals.
EMI Considerations
There are two possible sources of EMI on the X98021:
• Crystal oscillator. The EMI from the crystal oscillator is
negligible. This is due to an amplitude-regulated, low
voltage sine wave oscillator circuit, instead of the typical
high-gain square wave inverter-type oscillator, so there
are no harmonics. The crystal oscillator is not a significant
source of EMI.
• Digital output switching. This is the largest potential
source of EMI. However, the EMI is determined by the
PCB+ layout and the loading on the databus. The way to
control this is to put series resistors on the output of all the
digital pins. These resistor values should be adjusted to
optimize signal quality on the bus. Intersil recommends
starting with 22Ω and adjusting as necessary for the
particular PCB layout and device loading.
Recommendations for minimizing EMI are:
• Minimize the databus trace length
• Minimize the databus capacitive loading.
If EMI is a problem in the final design, increase the value of
the digital output series resistors to reduce slew rates on the
bus. This can only be done as long as the scaler’s setup and
hold timing requirements continue to be met.
Alternate Pixel Sampling
Two X98021s (AFEA and AFEB) may be used
simultaneously to achieve effective sample rates greater
than 210MHz. Each AFE is programmed with an HTOTAL
value equal to one-half of the total number of pixels in a line.
The CLOCKINVIN pin for AFEA is tied to ground, AFEB is
tied to VD. Both AFEs are otherwise programmed identically,
though some minor phase adjustment may be needed to
compensate for any propagation delay mismatch between
the two AFEs.
The CLOCKINVIN setting shifts the phase of AFEB by 180
degrees from AFEA. AFEA now samples the even pixels on
the rising edge of its DATACLK, while AFEB samples the odd
pixels on the rising edge of its clock. With each AFE in 24 bit
mode, two 24 bit data streams are generated (Figure 9).
With both AFEs configured for 48 bit mode, a 96 bit
datastream is generated (Figure 10).
In both cases, AFEA and AFEB are on different DATACLK
domains. In 24 bit mode, the data from each AFE must be
latched on the rising edge of that AFE’s DATACLK. In 48 bit
mode, the frequencies are low enough that the rising edge of
AFE B can be used to capture both AFEB and AFEA data.
23
FN8219.0
June 2, 2005