X98021 Datasheet, PDF (22/29 Pages) Intersil Corporation – 210MHz Triple Video Digitizer with Digital PLL

X98021
HSYNC_OUT
HSYNC_OUT is an unmodified, buffered version of the
incoming HSYNC_IN or SOG_IN signal of the selected
channel, with the incoming signal’s period, polarity, and
width to aid in mode detection. HSYNC_OUT will be the same
format as the incoming sync signal: either horizontal or
composite sync. If a SOG input is selected, HSYNC_OUT will
output the entire SOG signal, including the VSYNC portion,
pre-/post-equalization pulses if present, and Macrovision
pulses if present. HSYNC_OUT remains active when the
X98021 is in power-down mode. HSYNC_OUT is generally
used for mode detection.
VSYNC_OUT
VSYNC_OUT is an unmodified, buffered version of the
incoming VSYNC_IN signal of the selected channel, with the
original VSYNC period, polarity, and width to aid in mode
detection. If a SOG input is selected, this signal will output
the VSYNC signal extracted by the X98021’s sync slicer.
Extracted VSYNC will be the width of the embedded VSYNC
pulse plus pre- and post-equalization pulses (if present).
Macrovision pulses from an NTSC DVD source will lengthen
the width of the VSYNC pulse. Macrovision pulses from
other sources (PAL DVD or videotape) may appear as a
second VSYNC pulse encompassing the width of the
Macrovision. See the Macrovision section for more
information. VSYNC_OUT (including the sync separator
function) remains active in power-down mode. VSYNC_OUT
is generally used for mode detection, start of field detection,
and even/odd field detection.
HS_OUT
HS_OUT is generated by the X98021’s control logic and is
synchronized to the output DATACLK and the digital pixel
data on the output databus. Its trailing edge is aligned with
pixel 0. Its width, in units of pixels, is determined by register
0x19, and its polarity is determined by register 0x18[7]. As
the width is increased, the trailing edge stays aligned with
pixel 0, while the leading edge is moved backwards in time
relative to pixel 0. HS_OUT is used by the scaler to signal the
start of a new line of pixels.
The HSOUT Width register (0x19) controls the width of the
HS_OUT pulse. The pulse width is nominally 1 pixel clock
period times the value in this register. In the 48 bit output
mode (register 0x18[0] = 1), or the YUV input mode (register
0x05[2] = 1), the HS_OUT width is incremented in 2 pixel clock
(1 DATACLK) increments (see Table 7).
REGISTER
0x19 VALUE
0
1
2
3
4
5
6
7
TABLE 7. HS_OUT WIDTH
HS_OUT WIDTH (PIXEL CLOCKS)
24 BIT MODE, 24 BIT MODE, ALL 48 BIT
RGB
YUV
MODES
0
1
0
1
1
0
2
3
2
3
3
2
4
5
4
5
5
4
6
7
6
7
7
6
VS_OUT
VS_OUT is generated by the X98021’s control logic and is
synchronized to the output DATACLK and the digital pixel
data on the output databus. Its leading and trailing edges are
aligned with pixel 7 (8 pixels after HSYNC trailing edge). Its
width, in units of lines, is equal to the width of the incoming
VSYNC (see the VSYNC_OUT description). Its polarity is
determined by register 0x18[6]. This output is not needed in
most applications.
Macrovision
The X98021 will synchronize to and digitize Macrovision-
encoded YUV video if the source is an NTSC DVD.
Macrovision from PAL DVD, or from all video tape sources,
is incompatible with the sync slicer, requiring that the
Macrovision pulses either be stripped from the video prior to
the SOG_IN input, or an external COAST signal be generated
and applied to the CLKINV pin that will coast the X98021’s
PLL during the VSYNC and Macrovision period.
Standby Mode
The X98021 can be placed into a low power standby mode
by writing a 0x0F to register 0x1B, powering down the triple
ADCs, the DPLL, and most of the internal clocks.
To allow input monitoring and mode detection during power-
down, the following blocks remain active:
• Serial interface (including the crystal oscillator) to enable
register read/write activity
• Activity and polarity detect functions (registers 0x01 and
0x02)
• The HSYNC_OUT and VSYNC_OUT pins (for mode
detection)
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FN8219.0
June 2, 2005