X98021 Datasheet, PDF (25/29 Pages) Intersil Corporation – 210MHz Triple Video Digitizer with Digital PLL

X98021
HSYNC_IN
Conditions required: negative polarity VSYNC, with no serrations, and t₁ = t₂
t₁
t₂
FIGURE 11. CSYNC ON HSYNC THAT MAY CAUSE SPORADIC IMAGE SHIFTS
The output of the XOR gate is connected to the HSYNC_IN
input of the X98021. One of the XOR inputs is connected to
the HSYNC/CSYNC source, and the other input is
connected to a general purpose I/O. For all sync sources
except the CSYNC shown in Figure 11, the input connected
to the GPIO should be driven low.
If the system microcontroller detects a mode corresponding
to the sync type and polarity shown in Figure 11, it should
drive the GPIO pin high. This will invert the CSYNC signal
seen by the X98021 and prevent any spontaneous image
shifting.
X98021 Serial Communication
Overview
The X98021 uses a 2 wire serial bus for communication with
its host. SCL is the Serial Clock line, driven by the host, and
SDA is the Serial Data line, which can be driven by all
devices on the bus. SDA is open drain to allow multiple
devices to share the same bus simultaneously.
Communication is accomplished in three steps:
1. The Host selects the X98021 it wishes to communicate
with.
2. The Host writes the initial X98021 Configuration Register
address it wishes to write to or read from.
3. The Host writes to or reads from the X98021’s
Configuration Register. The X98021’s internal address
pointer auto increments, so to read registers 0x00
through 0x1B, for example, one would write 0x00 in step
2, then repeat step 3 28 times, with each read returning
the next register value.
The X98021 has a 7 bit address on the serial bus. The upper
6 bits are permanently set to 100110, with the lower bit
determined by the state of pin 48. This allows 2 X98021s to
be independently controlled while sharing the same bus.
The bus is nominally inactive, with SDA and SCL high.
Communication begins when the host issues a START
command by taking SDA low while SCL is high (Figure 12).
The X98021 continuously monitors the SDA and SCL lines
for the start condition and will not respond to any command
until this condition has been met. The host then transmits the
7 bit serial address plus a R/W bit, indicating if the next
transaction will be a Read (R/W = 1) or a Write (R/W = 0). If
the address transmitted matches that of any device on the
bus, that device must respond with an ACKNOWLEDGE
(Figure 13).
Once the serial address has been transmitted and
acknowledged, one or more bytes of information can be
written to or read from the slave. Communication with the
selected device in the selected direction (read or write) is
ended by a STOP command, where SDA rises while SCL is
high (Figure 12), or a second START command, which is
commonly used to reverse data direction without
relinquishing the bus.
Data on the serial bus must be valid for the entire time SCL
is high (Figure 14). To achieve this, data being written to the
X98021 is latched on a delayed version of the rising edge of
SCL. SCL is delayed and deglitched inside the X98021 for 3
crystal clock periods (120ns for a 25MHz crystal) to eliminate
spurious clock pulses that could disrupt serial
communication.
When the contents of the X98021 are being read, the SDA
line is updated after the falling edge of SCL, delayed and
deglitched in the same manner.
Configuration Register Write
Figure 15 shows two views of the steps necessary to write
one or more words to the Configuration Register.
Configuration Register Read
Figure 16 shows two views of the steps necessary to read
one or more words from the Configuration Register.
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FN8219.0
June 2, 2005