82C85 Datasheet, PDF (7/21 Pages) Intersil Corporation – CMOS Static Clock Controller/Generator

82C85
The 82C85 S2/STOP, S1 and S0 control lines were
designed to detect a passive 111 state followed by a HALT
011 logic state before recognizing the HALT instruction and
stopping the system clocks. In the MAXimum mode, the
80C86/88 status lines go into a passive (no bus cycle) logic
111 state prior to executing a HALT instruction. The qualifi-
cation of a passive no bus cycle logic 111 state insures that
random transitions of the status lines into a logic 011 state
will not stop the system clock. This is necessary since the
status lines of the 80C86/88 transition through an unknown
state during T3 of the bus cycle.
Once the HALT instruction is decoded by the 82C85, either
the oscillator is stopped (STOP-OSCILLATOR mode F/C
tied low) or the external frequency source is gated off inter-
nally (STOP-CLOCK mode F/C HIGH). When the HALT
instruction is decoded with F/C low, the CLK and CLK50 will
be stopped in a logic high state after 2 additional cycles of
the clock. PCLK stops in it’s current state (high or low). This
is true for both SLOW and FAST mode operation. The HALT
instruction is detected in the same manner whether the
82C85 is in the SLOW or FAST mode.
Independent Stop Control for Minimum Mode Operation
When the 80C86 and 80C88 microprocessors are config-
ured in MINimum Mode (MN/MX pin tied high), their status
lines S0, S1, and S2 assume alternate functions. The logic
states and sequences (passive before a HALT) necessary
for automatic HALT detect in the 82C85 do not occur as in
the MAXimum mode. The 82C85 controller cannot use the
microprocessor status lines to detect a software Halt instruc-
tion when operating in MINimum mode.
However, the negative edge-activated S2/STOP pin pro-
vides a simple means for clock control in MINimum mode
80C86 and 80C88 systems. S2/STOP can be used as an
independent STOP control when S1 and S0 are held in the
logical HIGH state. Keeping the S0 and S1 inputs at a logic 1
level and transitioning S2/STOP from high to low will meet
the passive 111 state prior to a 011 state requirement of the
82C85. This feature allows 82C85 operation with the 80C86
and 80C88 in the MINimum mode, provides compatibility
with other static CMOS microprocessors and allows maxi-
mum flexibility in a system.
With S2/STOP being used as a stand-alone STOP com-
mand line, system clocks can be controlled via an 82C55A
programmable peripheral interface or other similar interface
circuits. This is accomplished by driving the S2/STOP input
with a PORT pin on the 82C55A (See Figure 1). The
82C55A port pin should be configured as an output and must
present a logic HIGH to the S2/STOP input for at least one
CLK cycle, followed by a LOW state. This will meet the
82C85 status input requirement of 111 followed by a 011.
When a logic 0 is written to a 82C55A port pin, the S2/ STOP
pin is pulled low, stopping the system clocks (CLK, CLK50,
PCLK). In essence, the 82C85 is software controlled via the
82C55A. As with the SLO/FST interface, PORT C is a logical
choice for this job since the individual bit set and reset com-
mands available for this port make control of the S2/STOP
input simple.
A START command issued to the 82C85 will override a
STOP command and the 82C85 will begin normal operation.
The low state of the negative-edge triggered S2/STOP input
will not prohibit the clocks from restarting. After a START or
RES command, the 82C85 must see a passive (111) state
followed by a HALT (011) state to stop the system clocks. To
accomplish this, the 82C55A port output must be brought
high and then returned low again for the 82C85 to recognize
the next STOP command.
External Decode Adds Halt Control
SS0, IO/M and DT/R can identify a MINimum mode 80C88
HALT execution. During T2 of the system timing (while ALE
is high), SS0, IO/M, and DT/R go into a 111 state when the
80C88 is executing a software HALT. These signals cannot
be tied directly to the S2/STOP, S1 and S0 inputs since they
are not guaranteed to go into a passive state prior to their
111 state. These signals can be decoded during the time
ALE is high to indicate a software HALT execution.
Slow Mode
When continuous operation is critical but power consump-
tion remains a concern, the 82C85 SLOW mode operation
provides a lower frequency at the CLK and CLK50 outputs
(crystal/EFI frequency divided by 768). The frequency of
PCLK is unaffected. The SLOW mode allows the CPU and
the system to operate at a reduced rate which, in turn,
reduces system power.
For example, the operating power for the 80C86 or 80C88
CPU is 10mA/MHz of clock frequency. When the SLOW
mode is used in a typical 5MHz system, CLK and CLK50 run
at approximately 20kHz. At this reduced frequency, the aver-
age operating current of the CPU drops to 200µA. Adding
the 80C86/88 500µA standby current brings the total current
to 700µA.
While the CPU and peripherals run slower and the 82C85
CLK and CLK50 outputs switch at a reduced frequency, the
main 82C85 oscillator is still running at the maximum fre-
quency (determined by the crystal or EFI input frequency.)
Since CMOS power is directly related to operating fre-
quency, 82C85 power supply current will typically be
reduced by 15-20%.
Clock Slow/Fast Operation
The SLO/FST input determines whether the CLK and CLK50
outputs run at full speed (crystal or EFI frequency divided by
3) or at slow speed (crystal or EFI frequency divided by 768)
(See Figure 4). When in the SLOW mode, 82C85 stop-clock
and stop-oscillator functions operate in the same manner as
in the FAST mode.
Internal logic requires that the SLO/FST pin be held low for
at least 195 oscillator or EFI clock pulses before the SLOW
mode command is recognized. This requirement eliminates
unwanted FAST-to-SLOW mode frequency changes which
could be caused by glitches or noise spikes.
To guarantee FAST mode recognition, the SLO/FST pin
must be held high for at least 6 OSC or EFI pulses. The
82C85 will begin FAST mode operation on the next PCLK
303