82C85 Datasheet, PDF (3/21 Pages) Intersil Corporation – CMOS Static Clock Controller/Generator

82C85
Pin Descriptions (Continued)
SYMBOL
RES
DIP PIN
NUMBER
17
RESET
16
CSYNC
1
AEN1
3
AEN2
7
RDY1
4
RDY2
6
ASYNC
21
READY
5
GND
9
V_CC
24
TYPE
I
O
I
I
I
I
I
I
O
I
I
DESCRIPTION
RESET IN: RES is an active LOW signal which is used to generate RESET. The 82C85 provides a
Schmitt trigger input so that an RC connection can be used to establish the power-up reset of proper
duration. RES starts crystal oscillator operation.
RESET: RESET is an active HIGH signal which is used to reset the 80C86 family processors. Its
timing characteristics are determined by RES. RESET is guaranteed to be HIGH for a minimum of
16 CLK pulses after the rising edge of RES.
CLOCK SYNCHRONIZATION: CSYNC is an active HIGH signal which allows multiple 82C85 and
82C84A to be synchronized to provide multiple in-phase clock signals When CSYNC is HIGH, the
internal counters are reset and force CLK, CLK50 and PCLK into a HIGH state. When CSYNC is
LOW, the internal counters are allowed to count and the CLK, CLK50 and PCLK outputs are active.
CSYNC must be externally synchronized to EFI.
ADDRESS ENABLE: AEN is an active LOW signal. AEN serves to qualify its respective Bus Ready
Signal (RDY1 or RDY2). AEN1 validates RDY1 while AEN2 validates RDY2. Two AEN signal inputs
are useful in system configurations which permit the processor to access two Multi-Master System
Buses.
BUS READY: (Transfer Complete). RDY is an active HIGH signal which is an indication from a de-
vice located on the system data bus that data has been received, or is available RDY1 is qualified
by AEN1 while RDY2 is qualified by AEN2.
READY SYNCHRONIZATION SELECT: ASYNC is an input which defines the synchronization
mode of the READY logic. When ASYNC is LOW, two stages of READY synchronization are pro-
vided. When ASYNC is left open or HIGH a single stage of READY synchronization is provided.
READY: READY is an active HIGH signal which is the synchronized RDY signal input.
Ground
V_CC: is the +5V power supply pin. A 0.1mF capacitor between V_CC and GND is recommended.
Functional Block Diagram
RES
(17)
START
(11)
CSYNC
(1)
SLO/FST
(12)
F/C
(19)
(20) ^EFI
X2
(22)
X1
(23)
RESTART
LOGIC
RESET PULSE
CONDITIONING
LOGIC
RESTART
EXTERNAL
FREQ.
SELECT
SYNC
LOGIC
SYNC
SPEED SELECT
DIV 256 OR DIV 1
MASTER
OSC
CLOCK
LOGIC
(DIVIDE
BY 3)
SELECTED
OSC
PERIPHERAL
CLOCK
(DIVIDE BY 6)
OSCILLATOR
S2/STOP
(15)
S1
(14)
S0
(13)
RDY1
(4)
AEN1
(3)
(7) ^AEN2
RDY2
(6)
ASYNC
(21)
STOP LOGIC
HALT
READY
SELECT
READY
SYNC
V_CC (24)
GND (9)
(16)
RESET
(8)
CLK
(10)
CLK50
(2)
PCLK
(18)
OSC
(5)
READY
299